North- Holland 97 Microprocessing and Microprogramming 22 (1988) 97 11 3 A General Real-Time Decoder Based on AMD2900 Devices Amjad Ali Soomro, Mushfiqur Rahman, and Sadiq M Sait. Department of Electrical Engineering, University of Petroleum and Minerals, Dhahran, Saudi Arabia A bit-slice microprocessor-based real-time decoder has been proposed in this paper. A microprocessor-based architecture is preferable because of its programability, availability, low cost and simplicity of design. Two strategies are adapted to increase throughput of the decoder for real-time decoding. First, bit-slice microprocessors are used and ALU word length is chosen to be equal to that of a code word. Second, decod- ing operation is accomplished in two steps, namely (1) Error detection and (2) Error correction. It takes relatively much longer time to correct errors. Therefore, a buffer memory is used to store incoming blocks as more than one block may be received during a decoding cycle. The design is versatile since different decoding algorithms can be executed by changing the microprogram. Minor, apparent and simple changes have to be made in the design to decode codes of longer block length. Keywords. Bit-slice devices, Coding, Decoding, Micropro- gramming, Universal AHPL. 1. Introduction In the early days of development of coding theory it became apparent that the real limit on the commu- nication rate was not set by Shannon's theorem [1] but by the complexity and cost of building de- coders. In fact, actual data rates attained were much less than those possible by Shannon's limit on channel capacity. Cyclic error-correcting codes are classes of codes in which every cyclic shifted version of a code word is also a valid code word. These codes can be repre- sented by a generator polynomial. Cyclic property of these types of codes has made possible the design of simple decoder structure using feedback shift registers. Most of the available literature on the realization of decoders for linear block codes deals with these kind of cyclic error-correcting codes. Other classes of codes exist, which are not cyclic but are considered to be good by virtue of their prop- erties, for example, code efficiency and error-cor- recting capability. Some efficient decoding algo- rithms for these codes exist but have remained in relative obscurity. This is due to the fact that their decoders cannot be realized using simple feedback shift registers. This results in elaborate circuitry off- setting the gains offered by these codes. Thus, cyclic codes have remained favorable over them. In this paper we propose a general microproces- sor-based decoder. The desire to use microproces- sors in the design of decoders stems from many rea- sons. The most important of these are: 1. programability 2. simplicity of the design 3. easy availability of microprocessors; and 4. low cost of the devices. Programability. Decoding algorithms are executed on the microprocessors by executing programs stored in memory. A different decoding algorithm can be executed on the same microprocessor-based architecture by rewriting the software, whereas a change in decoding algorithm in a hardware oriented design would require complete re-design of the system. In digital communication, the choice of a suitable code depends on various system constraints. These are channel bandwidth limitations, channel noise characteristics, data transmission rate, receiver complexity, cost effectiveness, etc. A microproces- sor-based architecture would make it possible to adapt the system with minimal changes to suit the requirements of a new code, or a different decoding algorithm, or both. A new code may require one or more ALU slices to be added, along with associated changes in bus width, memory word size, etc. If the decoding algorithm remains the same for the new