Germanium Nanowire Epitaxy: Shape and Orientation Control Hemant Adhikari, ² Ann F. Marshall, ‡ Christopher E. D. Chidsey, § and Paul C. McIntyre* ,²,‡ Department of Materials Science and Engineering, Geballe Laboratory for AdVanced Materials, and Department of Chemistry, Stanford UniVersity, Stanford, California 94305 Received November 11, 2005; Revised Manuscript Received December 19, 2005 ABSTRACT Epitaxial growth of nanowires along the 〈111〉 directions was obtained on Ge(111), Ge(110), Ge(001), and heteroepitaxial Ge on Si(001) substrates at temperatures of 350 °C or less by gold-nanoparticle-catalyzed chemical vapor deposition. On Ge(111), the growth was mostly vertical. In addition to 〈111〉 growth, 〈110〉 growth was observed on Ge(001) and Ge(110) substrates. Tapering was avoided by the use of the two- temperature growth procedure, reported earlier by Greytak et al. One-dimensional structures such as nanotubes and nanowires are being actively investigated for various applications in nanotechnology, including nanoelectronics. In the emerging technology of 3-dimensional (3D) nanoelectronics, vertically aligned nanowires have been proposed to provide a solution to attain ultrahigh-density nanoscale device arrays. Direct integration of vertical zinc oxide and indium oxide nanowires has been reported in which surround gate and top gate vertical field effect transistors were fabricated. 1,2 However, silicon and germanium-based nanowire devices are much more desirable for electronic and other applications because of their compatibility with existing Si CMOS integrated- circuit technology. Although, historically, Si replaced Ge in microelectronics largely because of the superior structural and electrical characteristics of the Si/SiO 2 interface, recent work on surface passivation of planar germanium surfaces and gate dielectric deposition on those surfaces suggests that Ge may again become an important material for high- performance transistors. 3,4 Germanium nanowire (GeNW) transistors are very promising components for active device layers above a single-crystal silicon substrate because of (a) their potential for high density arrays of devices, (b) the relatively low growth temperature (<400 °C) of these nanowires by catalyzed chemical vapor deposition making them compatible with 3D integrated circuits, and (c) the high intrinsic hole and electron mobilities of Ge compared to Si. The potential of GeNWs as building blocks for nanoscale 3D integrated circuits has been demonstrated by successful fabrication of field-effect transistors (FETs) based on p-type GeNWs with deposited high dielectric constant (high-k) films as gate insulators. 5 Most reported work to date has involved the growth of germanium nanowires from randomly placed catalysts on silicon oxide surfaces that give rise to randomly oriented nanowires. 6 Reported Si and Ge NW CVD growth directions include 〈111〉, 〈110〉, and 〈112〉. 7 Controlled crystal orienta- tion during growth of nanowires is a big challenge for the integration of nanowires into high-density 3D circuits. One way to achieve orientation control is epitaxial growth of the nanowires on a single-crystalline substrate. To the best of our knowledge, there is only one report to date of homoepi- taxial growth of GeNWs. 8 In that work, GeNWs were grown epitaxially on Ge(111) from a supersaturated Ge atomic vapor at 470-480 °C. There are other reports of heteroepi- taxial growth of germanium nanowires on Si(111) 9 and homoepitaxial growth of compound semiconductor InP(111)B nanowires on InP(111)B substrates. 10 In this paper, we report controlled epitaxial growth of GeNWs by Au-nanoparticle-catalyzed chemical vapor depo- sition from GeH 4 at temperatures of 350 °C or lower on Ge(111), Ge(110), Ge(001), and a Ge layer grown epitaxially on a Si(001) substrate. Such low growth temperatures are of interest for 3D integration of NWs with Si integrated circuits in order to avoid damaging preexisting metallization and dielectric passivation layers. The cold-wall CVD NW growth process reported here is compatible with modern semiconductor fabrication methods and avoids deposition on the walls of the growth chamber. We also report the use of the two-temperature growth procedure, originally reported by Greytak et al., 11 to avoid tapering of the nanowires, which is a serious problem for high-temperature NW growth by CVD. These results indicate that the range of process * Corresponding author. E-mail: pcm1@stanford.edu. ² Department of Materials Science and Engineering. ‡ Geballe Laboratory for Advanced Materials. § Department of Chemistry. NANO LETTERS 2006 Vol. 6, No. 2 318-323 10.1021/nl052231f CCC: $33.50 © 2006 American Chemical Society Published on Web 01/21/2006