IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 2, Ver. II (Mar. - Apr. 2015), PP 10-20 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-05221020 www.iosrjournals.org 10 | Page VLSI Implementation of Area Efficient Fast Parallel Fir Digital Filters Based On Fast Fir Algorithm S.Gopalakrishnan 1 , Dr.K.R.Valluvan 2 , Assistant Professor, Department of ECE, Shree Venkateshwara Hi-Tech Engineering College, Erode, India 1 . Professor & Head, Department of ECE, Velalar college of Engineering and Technology, Erode, India 2 . Abstract: This paper proposes new parallel fir structures to reduce the hardware complexity of higher order Finite Impulse Response (FIR) filter with symmetric coefficients based on Fast FIR Algorithms (FFAs). The objective is to design an area-efficient Fast Parallel Finite-Impulse Response (FIR) filter structure which constraint that the filter taps must be a multiple of 2 or 3. In this brief discussed for three parallel FIR Filter implementation based on recursively using proposed 2 parallel FIR Structure. It exploits the inherent nature of Symmetric co-efficient reducing the number of Multipliers in further. The parallel FIR filter structure based on proposed FFA techniques has been implemented based on Modified carry save adder (MCSA) for further enhancement. The reduction in hardware complexity is achieved by eliminating the bulky multiplier with an adder namely MCSA. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR structures, particularly when the length of the filter is very large. Keywords: Symmetric Filter; Polyphase decomposed Fast Finite Impulse Response (FIR) Algorithm (FFA); Common Sub expression Elimination (CSE) ; Level Constrained Common Sub expression Elimination (LCCSE) Parallel FIR symmetric convolution; Very Large Scale Integration (VLSI); FFA technique. I. Introduction The vital area of research in VLSI System Design is the area-efficient high-speed data path logic systems. Digital Filters are one of the most widely used fundamental devices in DSP systems, ranging from explosive growth in multimedia signal processing to wireless mobile communications. FIR filters are used in high frequency applications, like as multimedia signal processing, whereas some other applications require high throughput with a low-power circuit such as Multiple Input Multiple Output (MIMO) systems used in cellular wireless communications. A higher order digital filter is used video ghost canceller for broadcast television, it reducing the effect of multipath signal echoes. So higher order digital filter is unavoidable. Area complexity is optimized by reducing bulky multipliers from (2N - N/L) to L x N using the FFA technique. The Iterated Short Convolution (ISC) based linear convolution structure is transposed to obtain a new hardware efficient. i.e., Small-sized filtering structures recursively used to constructed large filters in [6]-[10]. This paper is organized as follows. A brief introduction of existing FFAs is shown in Section II. In Section III, the proposed new parallel FIR filter structures are presented. Section IV investigates the complexity analysis of an existing with proposed structures. In Section V, the description of hardware implementation and the experimental results are shown. Finally, section VII describes the conclusions and future work. I. Fast FIR Algorithm (FFA) In general the output of an n-tap FIR filter which can be expressed as in (1) N-1 y(n) = ∑ h (i). x(n-i) , n = 0,1,2,……,∞ …………..……... (1) i=0 where the input {x(n)} is an infinite-length input sequence of the length N FIR filter coefficients. Then, the traditional L-Parallel FIR filter can be expressed from polyphase decomposition as in [3]. L-1 L-1 L-1 . ∑ Y p (z L ). z -p = ∑ X q (z L )z -q ∑ H r (z -L )z -r ……………..……..(2) i=0 q=0 r=0 ∞ (N/L)-1 ∞ Where X q = ∑ z -k x (L k +q), H r = ∑ z -k X(L k +r) , Y p = ∑ z -k X(L k +p) for p,q,r = 0,1,2,……..L-1.