IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 3, Ver. I (May - Jun. 2015), PP 12-15 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-05311215 www.iosrjournals.org 12 | Page Quadrature Delta Sigma Modulator Design and Overview Samiksha Yadav #1 , Bhargav Panchal #2 , Gaurav Dhiman #3 #1 MTech student, ECE Department, VLSI Division, MODY University, Rajasthan #2 Senior Project Fellow (SPF), CSIR-CEERI Pilani, Rajasthan #3 Assistant Professor, ECE Department, MODY University, Rajasthan Abstract: Quadrature Band pass ADC is well known to be adopted in order to reduce the system complexity, increase integration and improve performance by digitizing the bandpass signal directly without prior conversion to baseband. The Quadrature sigma delta modulator is analyzed for different quantization level for the different parameters like Signal to noise distortion ratio, quantization noise rejection capability for various devices. The result highlights the analysis of different quadrature bandpass modulators which provides a good order modulator and help to enhance device efficiency. Keywords: Analog-to-digital conversion, bandpass delta-sigma modulator, Signal to Noise Ratio, Quantization Noise I. Introduction Considerable research effort pushes toward the realization of fully monolithic, chiefly digital, RF transceivers with the ultimate objective being the implementation of small, inexpensive, low-power communication devices that are robust, testable, and capable of handling multiple communications standards. Quadrature band-pass sigma-delta modulators are important building blocks for communication systems. Superheterodyne receivers often use quadrature mixers with complex signals that must be transformed into digital form. Often use quadrature mixers with complex signals that must be transformed into digital form sigma- delta converters are used with an aim of high level of reliability and functionality with reduced chip cost. Often zero IF solutions are unattractive because of the demanding image rejection requirements. Even low-IF for which the DC offset and the 1/f noise fall outside the signal band can be problematic for low power applications: the architecture must use wide-band A/D converters that are power hungry.[1] The solution is using quadrature or complex modulators that suppress the quantization noise only in the signal band and not the image band. This paper proposes a new design approach that locks the IF frequency to the clock frequency of the complex modulator. The accuracy of coefficients possibly influences the relative position of the zeros of the NTF but the notch is firmly defined. The proposed methodology is applied to different cases scheme and Simulation results indications on the possible circuit implementation are given. They can use in several applications like wireless, communication, medical .In these application multiple devices face the hurdle of SNR, NTF e.g. Digital Radio therefore the paper focuses on these wireless devices that require various parameters to improve its performance. This paper describes such an IC, which is a quadrature variant of a bandpass delta– sigma ∑∆ modulator. II. Theory General aspect: A conventional quadrature ∑∆ converter consists of an input branch, a loop filter and feedback branch.The main difference between the real and quadrature modulator is that the quadrature modulator operates on complex input samples and similarly the output is given in complex form. [2] A complex loop filter,employed in the quadrature modulator, can be realized as a complex integrator when considering the first order modulator .Higher order systems usually have multiple integrator includes . The main principle is similar as in a real integrator used in low pass ∑∆ modulators input sample are integrated over a unit delay the difference to a real system being that the samples are complex valued, as is the loop gain. Figure 1: Gernal quadrature delta sigma modulator