IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 3, Ver. I (May - Jun. 2015), PP 28-32 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-05312832 www.iosrjournals.org 28 | Page Design and Implementation of Low power Carry Select Adder Using Transmission Gate Logic Chandan Kumar Ray 1 , K.Srinivasarao 2. 1,2. (ECE Mewaruniversity, India) Abstract : Now A days power Reduction techniques play important Role in Low power VLSI Applications. Adder is digital circuit it performing addition operation used in many application like microprocessor and DSP In this paper Low power XOR gate has been designed using transmission gate logic, it is implemented carry select adder for low power VLSI application and compared with CMOS technology . The simulation is performed using a SPICE circuit simulator at 180nm technology node & 1.8V standard CMOS process. Comparison between these techniques has shown a significant power saving to the extent of 60% in case of Transmission gate logic design carry select adder , as compared to CMOS logic in 10- 100MHz transition frequency range. Keywords - Adder, carry select Adder , Mux , T_SPICE , XOR gate I. Introduction The increasing demand for Low power VLSI Application at Different Level like Circuit level, Architectural and Layout such way that low power reduction requirement plays very important role for portable devices and heat generated systems. Carry select adder is fast adder compared with other adder like ripple carry adder , carry save adder, carry skip adder but area is somewhat increased as compared with others. Now a days major problem is power dissipation and delay in ADDERS . So In this paper used transmission gate logic adder to achieve low power and less delay . The proposed circuit is the transmission gate logic XOR gate further implemented into 1_ bit carry select adder ,4_bit carry select adder and performance parameters like power, delay & power delay product were observed. Also it is compared with conventional CMOS logic circuit. Performance parameter curves shows that proposed circuit is efficient for low power application. This paper has been classified into six sections. Section II describes the working of XOR gate . Section III describes operation of 1_bit carry select adder Section IV describes 4_bit carry select adder Section V and VI are about simulation results and conclusion respectively II. XOR Gate Designed Using Transmission Gate When the two input are in one or zero at that time output is Zero and Reaming condition it is one from the figure 2.1 designed transmission gate , here total 8 transistor is used to achieve XOR gate function , In the case of CMOS technology 22 transistor used, for XOR gate function. From the graph 5.2 As we increased frequency power dissipation also increased . but In the case of transmission gate based XOR got the less power dissipation Truth table 1.1 A B Y 0 0 0 1 0 1 0 1 1 1 1 0