IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver. I (Jul - Aug. 2015), PP 31-36 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-05413136 www.iosrjournals.org 31 | Page LEAKAGE POWER REDUCTION TECHNIQUE IN CMOS CIRCUIT: A STATE-OF-THE-ART REVIEW Himanshu Asija 1 , Vikas Nehra 2 , Pawan Kumar Dahiya 3 1 (ECE Department, Govt. polytechnic, Sonipat, India) 2,3 (ECE Department, Deenbandhu Chhotu Ram University of Science & Technology, Murthal, India) Abstract: The demand for low power devices is increasing vastly due to the fast growth of battery operated applications such as smart phones and other handheld devices. It has become important to control the power dissipation throughout the design cycle beginning from the architectural level to final design at hardware level. Leakage current is the main factor which contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. More than 40% leakage in SRAM memory is due to leakage in transistors. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power. The various leakage power reduction techniques have been evolved to tackle the problem and it is still in progress. In this paper mainly, there is study of various leakage power reduction techniques with SRAM architecture in fabrication Technology. Keywords: CMOS, Dynamic Power, Leakage Control Transistor, SRAM, Sub-threshold Leakage Current, Threshold Voltage. I. Introduction Static Random Access Memory (SRAM) has played a key role in high performance and low power VLSI applications. SRAM is most common choice for embedded-memory CMOS Integrated Circuits (ICs) [1]. System speed, power consumption and stability are the main concern for the modern processors. Growing demand for battery power handheld multimedia systems are becoming more and more popular day by day. But Complementary Metal oxide Semiconductors (CMOS) technology has continuously scaled down so it has been a major thrust to improve the performance and robustness of the memory used in these devices [2]. The power-sensitive portable devices also confronted with the need to reduce the dynamic and standby power consumption to meet the stringent battery-life requirement [3]. Power consumption of SRAM is important for increasing mobile and handheld applications where battery life is key design [4]. There are basically two types of power dissipation: 1. Static power 2. Dynamic Power. In active mode of operation, leakage is due to both dynamic and static components. In the standby mode of operation, the power dissipation is due to standby leakage current. The static power of a CMOS circuit is determined by the leakage current through each transistor. Dynamic power consists of switching power, consumed while charging and discharging the loads on a device, and internal power (also referred to as short circuit power), consumed internal to the device while it is changing state. The reduction in leakage current can be achieved at both circuit and process-level techniques. At the process-level leakage reduction can be achieved by controlling the dimensions length, oxide thickness, junction depth and doping profile in the transistors [5]. At the circuit level, threshold voltage and leakage current of transistors can be effectively controlled by controlling the voltages of different device terminals [drain, source, gate and the body (substrate)].There are various proposed techniques to reduce the leakage power. A number of leakage reduction techniques have been proposed in previous works like multiple threshold voltage (MT-CMOS) or variable threshold voltage technologies (VT-CMOS), Leakage reduction by using dynamic V TH , Scaling supply voltage reduction, Leakage reduction by using Drowsy cache etc. The main contribution of the paper is to present a state-of-the-art review of the techniques adopted by researchers to reduce the leakage power in CMOS circuits. The rest of the paper is organized as under: Leakage mechanism in CMOS transistor is explained in Section II. Detailed survey of leakage reduction techniques is presented in Section III. Section IV explains six-transistor SRAM architecture. Leakage power reduction technique in SRAM cell is explained in Section V. Finally, the paper is concluded in the Section VI.