IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 31, NO. 6, JUNE 2012 941 A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, and Yervant Zorian, Fellow, IEEE Abstract —In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults. Index Terms—Linked faults, March test, random access mem- ory, static and dynamic faults, test generation. I. Introduction M ANY FUNCTIONAL fault models (FFMs) for static and dynamic random access memories (RAMs) have been introduced in the past. Specifically, static and dynamic FFMs were introduced in [1] and [2]. Further, a concept of linked functional fault models was developed [3]. Based on inductive fault analysis (IFA), their existence and importance in current memories was validated experimentally [4]–[12]. Earlier, an efficient test algorithm March SS of complexity 22N [1] and the minimal test algorithm March MSS of com- plexity 18N [13] were proposed for detection of all unlinked static faults. For detection of all linked and unlinked static faults test algorithm March SL of complexity 41N [3] was introduced. In [3], the class of all linked static faults was attempted for the first time to classify. However, they assumed erroneously that the number of all static linked faults was 480. In addition to the described linked faults, in [14] extra new 120 linked faults were described. Thus, it was assumed that the number of all static linked faults was essentially higher— 600. This was done based on introduction of the notion of “2-composite faults,” thus extending the notion of linked static faults and covering all linked and unlinked static faults. Correspondingly, in [14], a minimal test algorithm March MSL of complexity 23N was proposed for detection of all “2-composite” (linked and unlinked) static faults. Manuscript received June 15, 2011; revised October 6, 2011; accepted January 4, 2012. Date of current version May 18, 2012. This paper was recommended by Associate Editor C.-W. Wu. G. Harutyunyan and V. Vardanian are with Synopsys, Inc., Yerevan 0026, Armenia (e-mail: gharutyu@synopsys.com; vvardani@synopsys.com). S. Shoukourian is with the IT Educational and Research Center, Yerevan State University, Yerevan 0025, Armenia, and also with Synopsys, Inc., Yerevan 0026, Armenia (e-mail: samshouk@synopsys.com). Y. Zorian is with Synopsys, Inc., Mountain View, CA 94043 USA (e-mail: zorian@synopsys.com). Digital Object Identifier 10.1109/TCAD.2012.2184107 In [4], the authors showed the importance of dynamic faults for new static random access memory technologies. It has been shown [5], [6], [8] that dynamic faults can manifest themselves in many practical applications [15], [16] and development of test algorithms for their detection is important. In [10], the authors investigated thoroughly, both theoretically and practically, the nature and the root cause of dynamic faults based mainly on resistive open defects in memory circuits. Many dynamic faults were validated and the realistic ones were shown. The considered functional fault models are validated by us based on electrical circuit level analysis, customer feedbacks, and experiments on test chips. Different types of faults, including static and dynamic faults, address decoder faults, interport and intraport faults, process variation faults, and also linked static and dynamic faults were also considered. During test algorithm creation we pass through the follow- ing three major levels. 1) Layout to electrical circuit extraction: the extraction is done using memory structural information. 2) Electrical circuit to fault modeling extraction: the ex- traction is done using circuit level simulation. A com- prehensive set of faults are injected on electrical circuits (memory array, address decoder, sense amplifier, write driver) and are validated by the experiments. 3) Fault modeling to test algorithm extraction: the extrac- tion is performed using test algorithm generation tools. In [15], a minimal test algorithm March MD2 of complexity 70N was proposed for detection of all dynamic two-operation single-cell faults, as well as the subclass of two-operation two- cell dynamic faults where both of the sensitizing operations were applied either to the aggressor cell or to the victim cell. In [15] and [16], only these subclasses of dynamic faults were considered. The other two subclasses with two sensitizing operations to be applied sequentially, one to the aggressor (respectively, victim) cell and the other one to the victim (respectively, aggressor) cell, were not considered due to high complexity of the corresponding cases. If the memory scrambling is not available (this is the typical case) then the test algorithm has to consider all possible pairs of memory cells for completeness of testing, and the algorithm will have complexity quadratic with respect to the number of memory cells (words). Such algorithms are not feasible for testing large memories. 0278-0070/$31.00 c  2012 IEEE