Possibilistic Worst Case Distance and applications to circuit sizing Eva Sciacca 1 , Salvatore Spinella 2 , and Angelo Marcello Anile 1 1 Dipartimento di Matematica e Informatica, Università degli studi di Catania, Viale A. Doria 6, I 95125 Catania, Italy sciacca@dmi.unict.it 2 Consorzio Catania Ricerche, via A. Sangiuliano 262, I 95124 Catania, Italy spins@unical.it Abstract. The optimization methodology proposed in this work is inspired to [1] and is named Possibilistic Worst-Case Distance (PWCD). This scheme has been tested on an application related to the MOS device sizing of a two stage Opera- tional Transconductance Amplifier circuit (OTA) [2]. In order to model the uncer- tainties arising from circuit parameter simulations the fuzzy set theory, introduced by Zadeh [3], has been used. A linearization of the circuit performances as func- tion of circuit parameters has been fitted as suitable approximation in a finite range, this choice was suggested to reduce the computational cost related to simu- lations of the real design. By means of linearization the circuit performances were fuzzyfied and a possibility measure of performance failure was minimized. The proposed case study will show that the possibilistic approach to the worst case analysis, even though less accurate for indirect yield estimation with respect to the probabilistic one, can identify an optimal design in yield terms. Furthermore the possibilistic methodology allows to develop calculation without any statistical hy- pothesis or sensitive analysis. 1. Introduction The new technologies of MOS with shrinking dimensions have accelerated in the last decade and most likely they point at a typical dimension signifi- cantly lower than 80-100 nm in the next few years. Under 80-100 nm the process variations start to build-up and have a sizable effect on circuit's performances. Therefore the exploration of advanced circuits design is mandatory in order to anticipate the challenge of future behaviour of cir- cuit based on nanoscale CMOS devices. Examples of these challenges are parasitic, process variation and transistor reliability. It is necessary to have models for MOS devices able to predict accurately new physical effects arising from this miniaturization and easy to integrate into simulation flow.