Ageing of SiC JFET transistors under repetitive current limitation conditions M. Bouarroudj-Berkani a, * , D. Othman a,c , S. Lefebvre a , S. Moumen a,b , Z. Khatir b , T. Ben Sallah c a SATIE, CNAM, ENS Cachan, CNRS, UniverSud, ENS Cachan, 61 Av. du Président Wilson, 94234 Cachan, France b LTN INRETS, 25 allée des Marronniers – Satory – 78000 Versailles, France c LSE, Ecole Nationale d’Ingénieurs de Tunis, BP.37-1002-Tunis le Belvédère, Tunisia article info Article history: Received 2 July 2010 Accepted 13 July 2010 Available online 21 August 2010 abstract In power applications using normally on transistors, short circuit or current limitation modes can be recur- rent during operation, especially when powering converters. So, studying the robustness of these devices under such severe condition is an important issue. The paper presents ageing tests of normally on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit operations. Experimental tests are detailed and the evolution of electrical parameters during ageing is presented. Especially, the evolution during tests of ageing indicators like on-state resistance and saturation current is presented. Numerical investigations have been performed in order to estimate temperature during short circuit operation and to quantify the effect of the maximum temperature on the ageing process. Ó 2010 Published by Elsevier Ltd. 1. Introduction In high temperature applications context, and especially in the avionic one where ambient temperatures exceed 200 °C, the use of silicon carbide seems to be necessary to overcome the limits of silicon [1–4]. Previous results on SiC JFET transistors (normally on) have already shown high robustness to current limitation oper- ations and very good performances at very high temperature [5,6]. In many power electronic inverters for motor control, use of ‘‘normally on” transistors leads to high risk of short circuit opera- tions, especially when powering the converters or when gate drive defect occurs. During short circuit operation the transistor is work- ing in current limitation mode and undergoes very high power dis- sipation. Consequently, very fast temperature increase may occurs which can quickly lead to failure. These severe conditions are harmful for safety of converters. Previous studies have already shown the excellent robustness of SiC JFETs under these severe operation conditions in the case of a long term current limitation operation. For these studies, JFETs were used as current limiters with a gate-to-source voltage equal to zero [5,6]. This paper focuses on the behaviour of SiC JFETs under repetitive short circuit operations with a gate drive this time ap- plied to the transistors. Indeed, the use of ‘‘normally on” transistors can result in recurrent controlled short circuit operations when switching on converters (for example when gate drives are pow- ered by the power bus of the converter). Our objectives are to eval- uate the effect of short circuit repetition on the behaviour of the tested devices, to evaluate the number of short circuit operations a JFETs can withstand without failure and to point-out failure mechanisms by measuring ageing indicators. To this purpose, SiC JFET prototype transistors from SiCED (100 mX and 300 mX de- vices) have been tested under repetitive short circuit modes. Test vehicles are SiC single-chip attached to copper base plate with lead free solder in TO220 packaging. 2. Destructive tests 2.1. Test protocol description Experimental tests have been performed by subjecting the tran- sistors to repetitive short circuit using the dedicated test bench shown in Fig. 1. Device under test (DUT) is maintained in the on-state (V GS = 0 V) during the short circuit phase and switched-off by reverse biasing the gate. A gate drive with voltage (V GS ) varying between 20 V and 30 V was developed for this purpose. The gate-to-source off-state voltage was adjusted according to both pinch-off and breakdown voltages of the gate–source junction for each tested de- vice. A gate resistance fixed to 47 X was used for this study. A circuit Breaker (1200 V IGBT) has been used in series with the DUT as a protection device. When the failure current exceeds I ref (arbitrarily fixed to 120 A) the IGBT is switched-off in order to avoid DUT explosion. Two different 1200 V transistors have been tested:  100 mX SiC JFET: V BR = 1200 V, R DSON = 100 mX, active area = 14 mm 2 .  300 mX SiC JFET: V BR = 1200 V, R DSON = 300 mX, active area = 3.95 mm 2 . 0026-2714/$ - see front matter Ó 2010 Published by Elsevier Ltd. doi:10.1016/j.microrel.2010.07.035 * Corresponding author. E-mail address: berkani@satie.ens-cachan.fr (M. Bouarroudj-Berkani). Microelectronics Reliability 50 (2010) 1532–1537 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel