IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 4, APRIL 2005 231 Three-Layer Laminated Metal Gate Electrodes With Tunable Work Functions for CMOS Applications W. P. Bai, S. H. Bae, H. C. Wen, S. Mathew, L. K. Bera, N. Balasubramanian, N. Yamada, M. F. Li, Senior Member, IEEE, and D.-L. Kwong, Senior Member, IEEE Abstract—This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate elec- trodes consisting of three ultrathin ( 1-nm) layers, with metal ni- trides (HfN, TiN, or TaN) as the bottom and top layers and ele- ment metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO , followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800 C–1000 C) drastically increased their work functions (as much as 1 eV for HfN–Ti–TaN at 1000 C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000 C. Index Terms—CMOS, laminated metal gate, metal gate, metal nitride, work function. I. INTRODUCTION A S CMOS devices are scaled beyond 100-nm nodes, metal gate electrodes are required to replace poly-Si gate in order to eliminate poly-depletion and boron penetration effects [1]–[3]. To achieve suitable threshold voltage for surface channel devices, gate electrodes must have suitable work func- tions . For conventional bulk CMOS devices, metal gates should have within 0.2 eV from the conduction and valence band edges of Si [4]. For nonbulk devices, which are more scalable due to effective suppression of short-channel effects, is required to be 0.3 eV above and below the midgap level (4.4–5.0 eV) [5]. From a process integration point of view, a metal gate process with work function tuning capability is highly desired. N ion implantation followed by thermal annealing was used to tune the work function of Mo with a range of 0.4 eV [6]. Intermixing/alloying by thermal annealing Manuscript received October 5, 2004; revised January 3, 2005. This work was supported in part by the MARCO Materials, Structures and Devices Focus Research Center and in part by the Texas Advanced Technology Program. The review of this letter was arranged by Editor C.-P. Chang. W. P. Bai, S. H. Bae, H. C. Wen, and D.-L. Kwong are with the Mi- croelectronics Research Center, Department of Electrical and Computer Engineering, the University of Texas at Austin, Austin, TX 78758 USA (e-mail: baiwp@mail.utexas.edu). S. Mathew, L. K. Bera, and N. Balasubramanian are with the Institute of Mi- croelectronics, Singapore. N. Yamada is with the ANELVA Corporation, Fuchu, Tokyo 183-8508, Japan. M. F. Li is with the Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore. Digital Object Identifier 10.1109/LED.2005.844701 Fig. 1. versus EOT plots of devices with HfN–Ta–TiN laminated metal gate electrode with high temperature RTA. and EOT were extracted from high frequency – measurements. of two layers of metals provides another approach. However, Ta-Pt, Ta-Ti [7], and Ni-Ti alloys [8], [9] showed poor thermal stability. Ru–Ta stacks [10] provided up to 0.4-eV reduction in work function compared to Ru but with significant increase of fixed charges during intermixing. In this letter, we propose the use of three-layer laminated metal stack gates for work function tuning for advanced CMOS applications. It is shown that these laminated metal gate elec- trodes on SiO offered significantly different work functions from their bulk metal counterparts and exhibited excellent thermal stability. II. DEVICE FABRICATION MOS capacitors and transistors were fabricated to charac- terize the laminated metal gates. The starting material was (100)-oriented p-type Si wafer with doping concentration around cm . In order to account for the influence of oxide fixed charge, SiO with different thicknesses ( 3, 6, and 8 nm) were thermally grown for work function extraction. Three ultrathin ( 1 nm) metal layers were in situ sputtered on SiO sequentially, with refractory metal nitrides (HfN, TiN or TaN) as the bottom layer and the top layer and element metals (Hf, Ti, or Ta) as the middle layer. A layer of 1000- TiN was then deposited as the capping layer. After gate patterning, these wafers were subjected to rapid thermal annealing (RTA) in N ambient at 800 C, 900 C, and 1000 C for 30 s or in forming gas at 400 C for 30 min. Devices with bulk (1200- -thick) metal gate electrodes (TaN, TiN, and HfN) were also fabri- cated for comparison. N-MOSFETs were patterned by one 0741-3106/$20.00 © 2005 IEEE