IEEE ELECTRON DEVICE LETTERS ,VOL. 24, NO. 10, OCTOBER 2003 631 Dual Work Function Metal Gates Using Full Nickel Silicidation of Doped Poly-Si J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong Abstract—This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi–SiO interface. No degradations on the underlying gate dielectrics are observed in terms of inter- face state density , fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing. Index Terms—Dopant, full silicidation, interface state density, metal gate, work function. I. INTRODUCTION M ETAL gate electrodes are required for future CMOS devices to replace poly-Si in order to solve problems of poly-depletion effects and boron penetration. The appropriate threshold voltages (Vt) require the work functions of metal gates ranging from 4.1–4.4 eV for NMOS and 4.8–5.1 eV for PMOS [1]. In order to optimize Vt in high-performance devices, the metal gates need tunable work function for NMOS and PMOS devices in CMOS process similar to present poly-Si gate technology. Metal interdiffusion gate (MIG) based on diffusion between two metals during thermal reaction, yields two work function values that are strongly dependent on the metal material properties [2]. Work functions can also be tuned by introducing nitrogen implantation to a single metal [3]. Self-aligned silicide (SALICIDE) technology has been used in advanced CMOS process, in which only partial poly-Si gets silicided. [4] [5]. The extension of existing SALICIDE tech- nology into fully silicided gates has several advantages from a processing point of view, and its low temperature formation is CMOS compatible. Recently, several fully silicided metal gates have demonstrated poly-depletion reduction and lower sheet resistance [6]–[8]. CoSi FUSI shows a single mid-gap work function with N and P poly-silicon while NiSi has shown tunable work functions [6]–[8]. The effects of poly-Si doping concentration on NiSi work function was studied for both FinFETs and FDSOI devices [8]. Arsenic pile-up at the Manuscript received June 17, 2003; revised July 18, 2003. The review of this letter was arranged by Editor B. Yu. J. H. Sim, H. C. Wen, and D. L. Kwong are with the Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78758 USA (e-mail: jangsim@mail.utexas.edu). J. P. Lu is with the Silicon Technology Development, Texas Instruments, Dallas, TX 75243 USA. Digital Object Identifier 10.1109/LED.2003.817372 NiSi–SiO interface was reported in [7] and suggested to be the cause for NiSi work function modification. In this paper, we investigate the effects of poly-Si dopants on the NiSi FUSI process and work function tuning by comparing As-, B-, and undoped fully silicided (FUSI) NiSi gates using the same p-Si substrates. In addition, the effects of NiSi FUSI on the electrical properties of underlying gate dielectrics are studied, including interface state density, fixed oxide charges, leakage current, and breakdown voltage. II. EXPERIMENT NiSi FUSI NMOS capacitors with three different oxide thick- nesses (2.5, 3.5, and 6.5 nm) were fabricated on P-type sub- strates. 80-nm poly-Si film was deposited and implanted with As (40 keV cm ) or B (5 keV cm ), followed by spike activation anneal at 1050 C. For compar- ison, undoped poly of 80-nm-in thickness was also fabricated on identical gate oxides. 60-nm-Ni thickness was then deposited on poly-Si and a gate pattern was made, forming capacitors with an area of cm . FUSI process was performed using RTA at 500 C in N , followed by removal of unreacted Ni using SPM solution (H O : ). Capacitance–voltage (C–V), current–voltage (I–V), and interface characteristics of the NiSi-gated capacitors were measured to examine the FUSI process and how they are affected by poly-Si dopants. XPS depth-profiling was taken to study dopant distribution during FUSI process and resulting NiSi composition. XTEM was used to confirm FUSI and exam the NiSi–SiO interface properties. III. RESULT AND DISCUSSION XTEM of Ni (600 )–n -poly–SiO –Si after FUSI process is shown in Fig. 1(a). As can be seen, Fig. 1(a) shows a 500 C, 20 s annealing is sufficient to achieve FUSI with an excellent NiSi–SiO interface. Full silicidation was also observed under the same FUSI condition for B-doped and undoped samples. shifts are observed in the C–V curves of these devices accom- panying with increase in accumulation capacitance, confirming the work function modification as well as the elimination of poly-depletion as a result of FUSI. The time dependence of NiSi FUSI formation process at 500 C is shown in Fig. 1(b) in which the accumulation capacitance values of NiSi–SiO devices are plotted as a function of RTA annealing time for undoped as well as B- and As-doped poly-Si. As can be seen clearly, the accumu- lation capacitance remains constant after 500 C 20 s annealing for all devices, suggesting that FUSI is completed within 20 s anneal and FUSI formation is independent of dopants in poly-Si. 0741-3106/03$17.00 © 2003 IEEE