90 zyxwvutsrqponmlkjihgf IEEE TRANSACTIONS ON ELECTKON DEVICES, VOL. 43, NO. 1, JANUARY 1996 A Computationally Efficient Model for version Layer Quantization Effects in Submicron N-Channel MOSFET’ s Scott A. Hareland, zyxwvutsrqp Student Member, IEEE, Shyam Kzlshnamurthy, Snnivas Jallepalli, Student Member, IEEE, Choh-Fei Yeap, Khaled Hasnat, AI F. Tasch, Jr,, Fellow, IEEE, and Christine M. Maziar Member, IEEE, Abstract-Successful scaling of MOS device feature size re- quires thinner gate oxides and higher levels of channel dop- ing in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (50.25 pm gate length) technology, the combination of the extremely thin gate oxides zyxwvutsrq (tax 5 10 zyxwvuts nm) and high channel doping levels results in transverse electric fields at the zyxwvutsrqp Si/SiOz interface that are sufficiently large, eve= near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quan- tum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in today’s widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that pre- dicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors. I. INTRODUCTION HROUGHOUT the history of integrated circuit design, a general scaling methodology has been appIied and has facilitated rapid and orderly transition from one technology generation to the next. This scaling methodology relies heavily on the use of successively thinner gate dielectrics and higher levels of channel doping as feature sizes decrease in order to simultaneously achieve the desired device turn-off and drive current capabilities [l], [Z]. As gate lengths approach deep submicron dimensions (50.25 pm), the device design, as guided by scaling, can result in very large transverse electric Manuscript received June 12, 1995; revised August 17, 1995. The review of this paper was arranged by Associate Editor A. H. Marsh&. This work was supported in part by the Semiconductor Research Corporation (SRC), the Texas Advanced Technology Program, Motorola, AMD, Micron Semiconduc- tor, and VLSI Technology. The authors are with the Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78712 USA. Publisher Item Identifier S 0018-9383(96)00257-2. fields at the Si/SiOz interface, even near the threshold of inversion. This leads to significant bending of the energy bands at the Si/SiOz interface. It has been long known that with sufficient band bending, the potential well can become sufficiently narrow to quantize the motion of inversion layer carriers in the direction perpendicular to the interface [3]-[6]. This gives rise to a splitting of the energy levels into subbands (2-D density of slates), such that the lowest of the allowed energy levels for electrons in the well does not coincide with the bottom of the conduction band. Many of the early investigations of quantum effects were focused on understanding the physics and the examination of 2-D systems at low temperatures because there was no observable effect on device performance at room temperature compared to classical predictions which neglect quantum mechanical (QM) effects in the inversion layer. However, in room temperature deep submicron devices, these quantum effects manifest themselves through such measurable device parameters as the inversion layer charge density and resistance, threshold voltage, and the oxide thickness extracted from capacitance vs. voltage (C-V) or Fowler-Nordheim tunneling current measurements. It is important that the above mentioned inversion layer QM effects are accounted for in deep submicron device design. The use of the traditional, or classical, models in device analysis and design, in which these effects are neglected, is inadequate at deep submicron dimensions and will lead to erroneous and misleading predictions of the device structure and electrical behavior, such as the physical oxide thickness, threshold voltage, drive current, capacitance, on-state series resistance, and the polysilicon workfunction. The two-dimensional nature of electrons in inversion lay- ers has been studied in detail by a number of researchers [5]-[SI by solving Schrodinger’s and Poisson’s equations self-consistently. Self-consistent solutions can be obtained by coupling Schrodinger’s equation to traditional balance equations. However, this is very much more computationally expensive than are simpler drift-diffusion simulations. In this paper, two approximate and computationally efficient models for electron inversion layer quantization are discussed. These models have been implemented into a commonly used drift- diffusion simulator, PISCES [9], and the results are compared to data from self-consistent Schrodmger-Poisson calculations 0018-9383/96$05.00 zyxwvut 0 1996 IEEE