IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 4, APRIL 2009 595 Performance-Aware Corner Model for Design for Manufacturing Chung-Hsun Lin, Member, IEEE, Mohan V. Dunga, Darsen D. Lu, Ali M. Niknejad, and Chenming Hu, Fellow, IEEE Abstract—We present a methodology to generate performance- aware corner models (PAMs). Accuracy is improved by empha- sizing electrical variation data and reconciling the process and electrical variation data. PAM supports corner (±σ and ±2σ) simulation and Monte Carlo simulation. Furthermore, PAM sup- ports the practice of application-specific corner cards, for exam- ple, for gain-sensitive applications. Index Terms—Compact model, corner model, Monte Carlo (MC), variations. I. INTRODUCTION I N THE sub-45-nm CMOS technology regime, the impact of device variations on circuit functionality becomes critical. The scaling of the device geometry makes device characteristics more sensitive to the fluctuations of wafer processing. This leads to a greater variance of device/circuit performance around the nominal design target. The statistical compact modeling be- comes crucial for accurately predicting the statistical variations of VLSI circuit performance such as speed, leakage power, and gain. It is also desirable to predict the performance yield of the circuit from the information on process variations. The major challenge of statistical circuit performance analy- sis is how to relate the device-level variation to the circuit-level variation in an accurate and efficient manner. Two conventional approaches for simulating the impact of device variation on circuit performance are as follows: 1) corner-model method and 2) Monte Carlo (MC) SPICE simulation [1]. The corner method is simple, computationally efficient, and thus widely adopted by circuit designers. However, the corner approach usually gives overly pessimistic or optimistic performance prediction due to insufficient attention to the quantitative correlations between the corner models and the circuit performance variations. The MC SPICE provides more accurate prediction using statisti- cal information but is computationally expensive for complex VLSI circuits. In addition, the accuracy of the MC approach depends on the accuracy of the variations of the SPICE model Manuscript received June 26, 2008; revised November 17, 2008. Current version published March 25, 2009. This work was supported in part by SRC under Grant 1451.001 and in part by the UC Discovery Grant ele07-10283 through the IMPACT program. The review of this paper was arranged by Editor V. R. Rao. C.-H. Lin is with the IBM TJ Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: linc@us.ibm.com). M. V. Dunga is with SanDisk, Milpitas, CA 95035 USA. D. D. Lu, A. M. Niknejad, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-1770 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.2011845 parameters. The latter accuracy can be improved with greater attention paid to the ET variation data [2]. Principal component analysis (PCA) was introduced to cap- ture the complex correlations of device parameters [3]. PCA transforms the correlated device parameters into uncorrelated variable (principal component). Each device parameter is a linear or nonlinear combination of the principal components. There is no physical interpretation of these principal compo- nents. However, the accuracy of PCA can be problematic in nanoscale CMOS technology due to highly nonlinear device characteristics and heterogeneity of device parameter patterns [4]. To overcome this issue, an ET-based direct sampling methodology (DSM) extracts device model parameters for all test sites and preserves the existing complex nature of param- eter correlations [4], [5]. DSM can predict more accurate distribution of circuit performance due to stochastic process variations. However, the accuracy of the DSM relies on the number of generated device parameter sets. The more generated parameter sets lead to more accurate predicted results. The effi- ciency of the device parameter extraction for significant number of test sites could be problematic due to a more complex process introduced in the advanced CMOS technology. Backward prop- agation of variance approach [6] was introduced to model the process variations based on physical process parameters and the propagation of the variance. The model is efficient and general for all kinds of variability studies. However, the model requires a very accurate nominal SPICE model card with correct sensitivities to different process parameters. In addition, the model does not account for nonlinearities of the sensi- tivity, which could lead to inaccurate results when variations are large. This paper first presents an improved methodology for de- termining the variations of the SPICE model parameters from physical parameter (L g , T ox , etc.) variations and ET data (V th , I on , I off , R out , etc.) variations. The improved set of model parameter variations will directly improve the accuracy of MC circuit simulations. Furthermore, this paper proposes a method of generating performance-aware (corner/distribution) model (PAM) cards. More accurate and application-specific (for speed, power, gain, etc.) model cards can be easily gener- ated at any distribution or yield levels (such as +2σ and −1σ). The details of how to combine the information on the vari- ances of the physical parameters and ET data to determine the SPICE model parameter variances are presented in Section II. The methodology of generating the PAM cards is discussed in Section III. In Section IV, we demonstrate the accuracy improvement of the generated PAM cards by applying them to example logic circuit. A subset of the PAM card generation 0018-9383/$25.00 © 2009 IEEE