Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits Adrian Stoica, Didier Keymeulen’, Raoul Tawel, Carlos Salazar-Lazaro, and Wei-te Li Jet Propulsion Laboratory California Institute of Technology Pasadena, CA 9 1109 adrian.stoica@jpl.nasa.gov Abstract The paper describes the architectural details of a fine- grained Programmable Transistor Array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. A PTA chip was built in CMOS to allow circuits obtained through evolutionary design using a simulated PTA to be immediately deployed and validated in hardware and, moreover, enables a benchmarking and comparison of evolutions carried out via simulations only (extrinsic evolution) with the chip-in-the-loop (intrinsic) evolutions. The evolution of an analog computational circuit and a logical inverter are presented. Synthesis by sofiare evolution found several potential solutions satisfiing the a- priory constraints; however, only a fraction of these proved valid when ported to the hardware. The circuits evolved directly in hardware proved stable when ported to different chips. In either case, both software and hardware experiments indicate that evolution can be accelerated when gray-scale (as opposed to binary switches) were used to define circuit connectivity. Overall, only evolution directly in hardware appears to guarantee a valid solution. 1 Introduction Evolvable Hardware (EHW) is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. The search foran electronic circuit realization of a desired transfer characteristic can be made in software as in extrinsic evolution, or in hardware as in intrinsic evolution. In extrinsic evolution the final solution is downloaded to (or become a blueprint for) the hardware. In intrinsic evolution the hardware actively participates in the circuit evolutionary process. I Also member of the Electrotechnical Laboratory, Tsukuba, Japan. In the context of electronic synthesis on reconfigurable devices, the architectural configurations are encoded in “chromosomes” that define the state of the switches connectingelements in thereconfigurablehardware.The main steps in evolutionary synthesis of electronic circuits are illustrated in Figure 1. First, a population of chromosomes is randomly generated to represent a pool of circuit architectures. The chromosomes are converted into circuit models (for extrinsic EHW) or control bitstrings downloadedtoprogrammablehardware (intrinsic EHW). Circuit responses are compared against specifications of a target response and individuals are ranked based on how close they come to satisfying it. Preparation for a new iteration loop involves generation of a new population of individuals from the pool of the best individuals in the previousgeneration.Here,someindividuals are takenas they were and some are modified by genetic operators, such as chromosome crossover and mutation. The process is repeated for a number of generations, resulting in increasingly better individuals. The process is usually ended after agivennumberofgenerations, or whenthe closeness to the target response has been reached. In practice, one or several solutions may be found among the individuals of the last generation. A variety of circuits have been synthesized through evolutionary means. For example, Koza used Genetic Programming (GP) to grow an “embryonic” circuit to one that satisfies desired requirements [l]. This approach was used for evolving a variety of circuits, including filters and computational circuits. An alternative encoding technique for analog circuit synthesis, which has the advantage of reduced computational load was used in [2] for automated filter design. On-chip evolution was demonstrated by Thompson [3] using an FPGA as the programmable device, and a Genetic Algorithm (GA) as the evolutionary mechanism. More details on current work in evolvable hardware are found in [4], [5], [6], and [7].