IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 8, AUGUST 2012 427 A 27–41 GHz Frequency Doubler With Conversion Gain of 12 dB and PAE of 16.9% Jiankang Li, Yong-Zhong Xiong, Senior Member, IEEE, Wang Ling Goh, Senior Member, IEEE, and Wen Wu, Senior Member, IEEE Abstract—A 27–41 GHz monolithic balanced frequency dou- bler fabricated using the 0.13 SiGe BiCMOS technology is presented in this letter. The balanced doubler consists of a balun, a driver amplifier (DA), a common-base (CB) doubling core and a medium power amplifier. The CB topology is used to increase the bandwidth and for the ease of matching with the balun. The proposed frequency doubler attained a measured gain of 16.8–19.8 dB, an output power of 1.3–4.3 dBm, and a fundamental rejection of better than 25.7 dB (from 27 to 41 GHz) at an input power of . An maximum output power of 8 dBm with dc power consumption of 35 mW and corresponding power added efficiency (PAE) of 16.9% have also been achieved. The chip size is 0.75 mm 0.45 mm. Index Terms—Balanced frequency doubler, high efficiency, high output power, SiGe BiCMOS. I. INTRODUCTION W ITH the continuous increase in the wireless communi- cation operating frequency, the design of fundamental voltage control oscillator (VCO) with wide tuning range and good phase noise becomes even imperative and challenging. In order to relax the requirements of VCO, a popular approach for ensuring a higher frequency source is to multiply from the lower frequency source. Thus, broadband frequency doublers with high conversion gain and high efficiency are desired in the microwave and millimeter-wave communication systems. Frequency doublers implemented using Si-based processes [1]–[6] have been demonstrated recently. A reported single-end doubler consisting of a common-source doubler cascaded to a cascode amplifier demonstrated a conversion gain of between and 0 dB, from 18 to 26 GHz output frequency [1]. In many cases, the balanced topology is adopted to realize a broadband fundamental rejection and a high output power. A SiGe HBT Manuscript received January 09, 2012; revised March 27, 2012; accepted June 04, 2012. Date of publication July 05, 2012; date of current version August 03, 2012. J. Li is with the Ministerial Key Laboratory of JGMT, School of Electronic and Optical Engineering, Nanjing University of Science and Technology, Nan- jing, 210094, China and also with MicroArray Technologies, Chengdu 611731, China (e-mail: jkli022@163.com). Y.-Z. Xiong was with the Institute of Microelectronics of Singapore, Sin- gapore 117685. He is now with MicroArray Technologies, Chengdu 611731, China (e-mail: eyzxiong@ieee.org). W. L. Goh is with the School of Electrical and Electronic Engi- neering, Nanyang Technological University, Singapore 639798 (e-mail: ewlgoh@ntu.edu.sg). W. Wu is with the Ministerial Key Laboratory of JGMT, School of Electronic and Optical Engineering, Nanjing University of Science and Technology, Nan- jing 210094, China. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2012.2205228 Ka-band balanced frequency doubler has a conversion gain of 3–4.5 dB and a fundamental rejection of 35 dB from 34.6 to 37.6 GHz output frequency [2]. The Gilbert-cell structure too can be used in the balanced doubler [3]. Moreover, a balanced SiGe BiCMOS frequency doubler with active balun and dis- tributed amplifier had also been presented [4]. In this letter, a balanced common-base (CB) doubler is fab- ricated in a commercial 0.13 SiGe BiCOMS technology by combining three methodologies: a) the CB doubler is adopted to extend the bandwidth and for easy integration with the balun; b) the differential balanced topology is used to achieve broad- band fundamental rejection; and c) the medium power amplifier is employed for attaining higher output power and power-added efficiency (PAE). The proposed balanced doubler is able to de- liver a high conversion gain, high PAE and good fundamental rejection from 27 to 41 GHz. II. CIRCUIT DESIGN The process involves seven metal layers, and this includes the two top thick metal layers. From the bottom metal layer, an silicon dioxide layer that can provide better electrical performance for passive components allows the passive balun to be adopted in our design. Fig. 1 shows the schematic of the proposed frequency doubler which consists of a driver ampli- fier (DA), a common-base doubling core and a medium power amplifier (PA). Here, the DA is used to amplify the input signal hereby relaxing the power requirement of the front-end VCO. Following that, the single-ended signal is split into differential signals by the balun, and these two differential signals are fed into the differential CB doubling core that involves a differen- tial CB amplifier and a cascade buffer for generating the second harmonic signal. The last stage is the medium PA for delivering a larger power, a stable gain and also for output port matching. In this design, the transformer balun is deployed for signal splitting, which requires no dc power. This permits a compact structure as compared to the Marchand balun [5]. The proposed structure is also able to provide impedance matching and the necessary dc supply for transistors , and in Fig. 1. The circuit, however, does exhibit minute dependence on the temperature, i.e., the electrical performance, as opposed to ac- tive balun. The 3-D simulation model of the adopted balun is provided in Fig. 2(a). This 2-turns overlay balun is designed on the two top thick metal layers with a width of 6 , a spacing of 4 and an inner diameter of 90 . The differential input signals are fed into the emitter of tran- sistors, and , where both are biased near the class-B re- gion ( ) so as to generate the second harmonic signal efficiently [6]. In the common emitter (CE) doubling configura- tion, the midpoint ( ) of the balun is very often connected to 1531-1309/$31.00 © 2012 IEEE