Electronic structure at interfaces of cubic Gd 2 O 3 with embedded Si nanocrystals M. Badylevich a, * , S. Shamuilia a , V.V. Afanas’ev a , A. Stesmans a , A. Laha b , H.J. Osten b , A. Fissel c a Department of Physics and Astronomy, INPAC – Institute for Nanoscale Physics and Chemistry, University of Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium b Institute of Electronic Materials and Devices, Leibniz University, Appelst. 11A, D-30167 Hannover, Germany c Information Technology Laboratory, Leibniz University, Schneiderberg, 32, D-30167 Hannover, Germany article info Article history: Received 17 June 2008 Accepted 3 September 2008 Available online 12 September 2008 Keywords: Nanocrystals Insulator Band alignment Bandgap width abstract The electronic structure of silicon nanocrystals (2–6 nm in size) embedded in cubic Gd 2 O 3 epi-layers grown on (1 1 1) Si was analyzed using spectroscopic ellipsometry and photocharging methods. With decreasing nanocrystal size down to the 2 nm range, the optical absorption exhibits a spectacular shift in spectral threshold to 2.9 ± 0.1 eV, as compared to the 1.12 eV absorption edge of the bulk Si crystal. This shift suggests a significant influence of quantum confinement on the Si nanocrystal/oxide interface band diagram, which effect is shown to be predominantly caused by an upshift of the nanocrystal conduction band. Ó 2008 Elsevier B.V. All rights reserved. 1. Introduction Modernnon-volatilememorydevicesstorechargesinapolysilicon or silicon nitride trapping layer that can be charged or discharged by applyingagatevoltage.Replacingthechargetrappinglayerwithanar- ray of silicon nanocrystals (ncs) embedded in a dielectric matrix pro- vides the possibility to increase the storage density and data retention [1,2]. Traditionally, silicon dioxide has been used as the dielectric matrix of choice for floating gate memory devices [1], but the device performance may further be improved by replacing the SiO 2 insulator by a material with higher dielectric constant (high-j) [3]. The potential of this approach has already been successfully dem- onstrated [4,5]. Among the high-j insulators envisioned, epitaxial Gd 2 O 3 has shown a great potential for application in silicon metal– oxide–semiconductor (MOS) devices [6] by offering not only a high dielectric constant but also interlayer-free interfaces, thus enabling an aggressive scaling of the gate stack. Additionally, epitaxial growth isapromisingwayofmakingathree-dimensionalarrangementofele- ments on a chip. One more benefit is that the epitaxial growth of the tunnel and field insulating layers enables nearly stress-free growth of Si ncs. The latter is of utmost importance to attain a quantum confine- ment regime because the strain induced by the surrounding matrix may not only affect the band states of the nc, but also promote formation of undesirable interface defects. In this work we exam- ined the possibility of realizing quantum confinement in Si ncs embedded into Gd 2 O 3 insulating layers epitaxially grown on (111) Si. 2. Experimental Structures of Gd 2 O 3 /Si-nc/Gd 2 O 3 were fabricated on n- and p- type (1 1 1) Si substrates using the solid source molecular beam epitaxy technique. Silicon and granular stoichiometric Gd 2 O 3 were evaporated by electron-beam heating with rates of 0.03–0.01 nm/s. The first epitaxial Gd 2 O 3 layer, serving as tunneling oxide, was grown at 675 °C on HF last-cleaned silicon surfaces under an oxy- gen partial pressure of 5  10 7 mbar as described elsewhere [7]. Subsequently Si was deposited on the epi-Gd 2 O 3 surface, where the temperature T during this deposition was the key parameter to control formation of ncs. As was shown previously [8], deposi- tion of Si at T > 400 °C leads to the growth of nm-sized single crys- tals of nearly spherical shape. Finally, the top Gd 2 O 3 layer (the field oxide) was deposited to form Si/Gd 2 O 3 /Si-nc/Gd 2 O 3 structures. De- tails of the growth procedure and size/shape characterization of the Si-ncs have been described before [8]. Three types of samples were analyzed – nc1, nc2, and nc3 – differing by the applied silicon deposition duration (3, 5 and 7 min, respectively) and conse- quently by the Si-ncs size. The experimental details concerning determination of ncs size in all samples will be given in the results and discussion section. The optical properties of the Si-nc samples were characterized using spectroscopic ellipsometry (SE) measurements in the photon energy range 1.6–6.2 eV (Sopra GES-5 Optical Platform). These were complemented by photocharging experiments carried out in the photon energy range 1.5–6.5 eV using metal-insulator- 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.09.002 * Corresponding author. Tel.: +32 16 327173; fax: +32 16 327987. E-mail address: Mikhail.Badylevich@fys.kuleuven.be (M. Badylevich). Microelectronic Engineering 85 (2008) 2382–2384 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee