Author's personal copy Integration of low dimensional crystalline Si into functional epitaxial oxides Apurba Laha a,Ã , E. Bugiel a , R. Dargis a , D. Schwendt a , M. Badylevich b , V.V. Afanas’ev b , A. Stesmans b , A. Fissel c , H.J. Osten a a Institute of Electronic Materials and Devices, Leibniz University of Hannover, Appelstr.11A, D-30167 Hannover, Germany b Department of Physics and INPAC - Institute for Nanoscale Physics and Chemistry, University of Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium c InformationTechnology Laboratory, Leibniz University of Hannover, Schneiderberg 32, D-30167 Hannover, Germany article info Available online 25 July 2008 Keywords: Si quantum dots Oxide-semiconductor-oxide quantum well Nonvolatile memories Epitaxial gadolinium oxide Resonant tunneling diode abstract In this work we show that by efficiently exploiting the growth kinetics during molecular beam epitaxy (MBE) one could create Si nanostructures of different dimensions. Examples are Si quantum dots (QD) or quantum wells (QW), which are buried into an epitaxial rare-earth oxide, e.g. Gd 2 O 3 . Electrical measurements carried out on Pt/Gd 2 O 3 /Si MOS capacitors comprised with Si-QD demonstrate that such well embedded Si-QD with average size of 5 nm and density of 2  10 12 cm 2 exhibit very good charge storage capacity with suitable retention (10 5 s) and endurance (10 5 write/erase cycles) character- istics. The Pt/Gd 2 O 3 /Si (metal–oxide–semiconductor (MOS)) basic memory cells with embedded Si-QD display large programming window (1.5–2 V) and fast writing speed and hence could be a potential candidate for future non-volatile memory application. The optical absorption of such Si-QD embedded into epitaxial Gd 2 O 3 was found to exhibit a spectral threshold maximum up to 2.970.1 eV depending on their sizes, inferring a significant influence of quantum confinement on the QD/oxide interface band diagram. Ultra-thin single-crystalline Si-QW with epitaxial insulator (Gd 2 O 3 ) as the barrier layers were grown by a novel approach based on cooperative vapor phase MBE on Si wafer with sharp interfaces between well and barriers. The current–voltage characteristics obtained for such structure exhibits negative differential resistance at lower temperature, making them a good candidate for resonant tunneling devices. & 2008 Elsevier Ltd. All rights reserved. 1. Introduction Efficient integration of low dimensional crystalline Si nanos- tructures into a dielectric matrix, such as functional oxides could pave the way for large number of novel nanoscale device applications ranging from nonvolatile memories to next genera- tion solar cells. With immense fundamental interest in mind, such nanostructures could also set an example for studying various quantum phenomena in practical applications. As an example, Si quantum well with epitaxial Gd 2 O 3 as barrier layers could be used for unconventional quantum-effect device applications based on tunneling effects. Epitaxial gadolinium oxide (Gd 2 O 3 ) has also demonstrated a great potential for application as very thin high-K material replacing SiO 2 in future MOS devices. In particular, an ultra-thin epitaxially grown Gd 2 O 3 with CMOS- compatible FUSI NiSi gate electrode has been shown to meet ITRS targets for field effect transistors (FETs) for the near term schedule and beyond [1]. In this work we will show that the same epitaxial layer with embedded Si-quantum dots (Si-QD) can also be successfully used to realize novel devices such as nanocrystal memories, one of the promising candidates for future nonvolatile, high density, and low operating-voltage memory applications. Originally, this approach has been based on embedding single crystalline Si dots with few nanometers in size (Si-QD) into the insulating gate oxide of field effect transistor (FET), where Si-QDs could be used as deliberately generated trap centers for electrons and/or holes [2]. The entrapment of the charges (e.g. electrons) by these dots embedded in the gate oxide eventually shifts the threshold voltage during the device operation by screening the gate charges and hence reduces conduction in the channel inversion layer [2]. Electrical performance of these clusters strongly depends on their physical properties such as their size, density, and spatial distributions into the oxide as well. Thus, the most challenging task to improve the device perfor- mance has been the formation of nanostructures with constant size, high density, and uniform distribution. There are several approaches reported recently to place Si-nanostructures into SiO 2 and also high-K oxides [3–5]. Replacing SiO 2 with high-K oxide in floating gate memories is advantageous since the larger capaci- tance enhances the drive current while high breakdown voltage ARTICLE IN PRESS Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.06.064 Ã Corresponding author. E-mail address: laha@mbe.uni-hannover.de (A. Laha). Microelectronics Journal 40 (2009) 633– 637