IEEE JOURNAL zyxwvutsrqponmlkjihgfe ot SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988 59 Fast CMOS ECL Receivers With 100-mV Worst-case Sensitivity zy Abstract -CMOS ECL receiver circuits consisting of a differential- amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1-pm technology. The same ECL receivers in submicrometer CMOS technology have higher speeds and better sensitivity, with smaller worst-case-to-best-case variations. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differen- tial mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying as- sumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process. Simulated and measured results demonstrate feasibility for 100-mV worst-case sensitivity for CMOS ECL receivers in 1-pm technology, with no substantial access- time penalty in going from TIL to zyxwvutsrqp ECL interfaces. I. INTRODUCTION MOS AMPLIFIERS in 5-V 1-pm CMOS technology C can serve as asynchronous receivers of high-speed ECL signals with 100-mV worst-case sensitivity. As the technology is scaled to submicrometer dimensions with reduced power supply voltages, these same receivers have even hgher speed and better sensitivity. CMOS ECL re- ceivers are needed for the small-signal interfaces required to use CMOS SRAM and logic in high-speed systems to the best advantage. CMOS SRAM’s are offering increasingly high-speed access times in addition to the well-known CMOS features of low power, robust operation, scalability, high density, and yield. Aggressive progress in MOS SRAM access time at the 64K level is evident from the Fig. 1 plot of access times versus year reported (see [1]-[5] for examples of the faster SRAM’s referenced in the figure). The trend line is every bit as steep at the 256K level and no doubt will Manuscript received July 31, 1987; revised September 23, 1987. B. A. Chappell, T. I. Chappell, S. E. Schuster, J. W. Allan, R. L. Franch, and P. J. Restle are with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. H. M. Segmuller was with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. He is now with the Westinghouse Defense and Electronics Center, Baltimore, MD. IEEE Log Number 8718033. zyxwvutsrqpon . 100 80 zyxwvutsr 256 Kb zyxwvu C 40 ._ ‘4. v) 10. 1 MbICMOS 256 Kb A CMOS 8! 64 KbmCMOS 6. 64 KboNMOS 78 80 82 84 86 88 90 Conference Reporting Year Progress in SRAM access time. Plot of access time as reported at conferences ([1]-[5]) for NMOS and CMOS SRAM with TTL interfaces. In the projected sub-10-ns access-time regime, chip-to-chip crossing delays could exceed on-chip delays if TTL interfaces continue to be used. Fig. 1. continue at 1 Mbit. With RAM’S in the sub-10-ns regime, however, use of l T L interfaces and networks can easily result in chip-to-chip crossing delays exceeding on-chip delays. Reduction of chip-to-chip crossing delays in large sys- tems through use of small-signal transmission-line net- works is a well-established art in the ECL bipolar world [6]. High-speed CMOS SRAM and logic can realize similar advantages if CMOS can be retrofit to a bipolar ECL environment or if conventional ECL standards can be adapted for use in all ’CMOS systems or modules. Either case involves designing CMOS off-chip drivers and termination schemes, among other wide-ranging issues. However, the design of asynchronous CMOS ECL re- ceivers having better than 100-mV worst-case sensitivity without adding substantially to the access time is one of the more difficult parts of the problem. The CMOS ECL receivers analyzed in this paper simply consist of a single differential amplifier stage with built-in compensation, followed by a CMOS inverter. Previously reported CMOS ECL receivers have used a much larger number of devices and complex bias and compensation schemes [7], [8]. The more complex circuitry is more sus- ceptible to mismatches in devices, power distribution, and noise. Additionally, the analysis becomes substantially more complicated as the number of devices grows and as they are distributed more widely in the physical layout of the chip. The analysis shown in this paper indicates that 0018-9200/88/0200-0059$01.00 01988 IEEE