ICTON 2011 Tu.D6.3 978-1-4577-0882-4/11/$26.00 ©2011 IEEE 1 Agile Photonic Integrated Systems-on-Chip Enabling WDM Terabit Networks Ch. Kouloumentas 1 *, M. Bougioukos 1 , M. Spyropoulou 1 , D. Klonidis 2 , G. Giannoulis 1 , D. Kalavrouziotis 1 , A. Maziotis 1 , P. Gkroumas 1 , D. Apostolopoulos 1 , P. Bakopoulos 1 , A. Poustie 3 , G. Maxwell 3 , K.O. Velthaus 4 , R. Kaiser 4 , L. Moerl 4 , I. Tomkos 2 , and H. Avramopoulos 1 1 National Technical University of Athens, 9 Iroon Polytechniou, Zografou, 15773 Athens, Greece 2 Athens Information Technology Center (AIT), 19,5km Markopoulou Av., 19002, Peania, Greece 3 CIP Technologies, Adastral Park, Ipswich, IP5 3RE, UK 4 Fraunhofer Heinrich Hertz-Institut, Einsteinufer 37, 10587 Berlin, Germany *Tel: (30210) 7722057, Fax: (30210) 7722077, e-mail: ckou@mail.ntua.gr ABSTRACT The ICT-APACHE research project is focusing on the development of cost-effective, compact, scalable and agile integrated components capable of generating, regenerating and receiving multi-level encoded data signals for high capacity (>100 Gb/s) WDM optical networks. APACHE technology relies on InP active, monolithic chips, hybridly integrated on silica-on-silicon planar lightwave platforms in order to achieve cost-efficiency, high yield, low power consumption and device scaling beyond the level commercially available today. The APACHE integration approach is implemented in a two-dimensional plan, horizontally and vertically, in order to enable multi-functionality and increased capacity, respectively. The final goal of the APACHE project is the fabrication of integrated arrays of transmitters, receivers and regenerators that will operate with 100 Gb/s OOK, DPSK and DQPSK modulated signals, allowing for 1 Terabit/s on-chip capacity. In this paper, we will review the latest results from the system-level characterization of the developed components and will outline the roadmap for future endeavours. Keywords: Monolithic arrays, hybrid integration, optical regeneration, advanced modulation formats. 1. INTRODUCTION – THE APACHE INTEGRATION CONCEPT Optical metro and core networks are evolving from point‐to-point high‐capacity links to dynamically re‐configurable networks driven by the traffic generated from new bandwidth‐hungry applications. Next generation optical networks should be capable of dynamically allocating bandwidth, setting‐up and tearing‐down lightpaths and providing more advanced real‐time resources allocation, evolving from static network topologies to re‐configurable networks that change and adapt according to bandwidth requirements. Within this context, the ICT-APACHE project [1] is aiming to extend this re-configurability in terms of bit-rate and modulation format by developing integrated arrayed photonic devices that are capable of simultaneously generating, processing and receiving amplitude- and phase-encoded optical signals for high capacity WDM optical networks. To develop these devices and achieve characteristics such as cost-effectiveness, high yield, small footprint, device scaling and low power consumption, APACHE is relying on the combination of high-speed indium phosphide (InP) monolithic elements, silicon submounts and ultra low-loss silica-on-silicon planar circuits. Through this “monolithic-on-hybrid” technology approach, low-loss passive assembly of different photonic elements (lasers, modulators, filters, waveplates) is achieved, allowing for enhanced complexity and functionality on board. In the present paper, we describe the main devices that are being developed within the project, we report on results from the experimental testing of assembled transmitter and regeneration devices, and we outline the future steps of the project activities. 2. DEVELOPMENT OF APACHE DEVICES – EXPERIMENTAL TESTING In the present section, we describe the fundamental concepts and the experimental results for the three types of APACHE arrayed devices (transmitters, all-optical processors, receivers). 2.1 WDM Transmitters APACHE is pursuing two main integrated transmitter modules: (1) Multi-format transmitter for on-off keying (OOK), differential phase-shift keying (DPSK) and differential quadrature phase-shift keying (DQPSK) formats with 1 Tb/s capacity and application in core networks, and (2) low- cost reflective semiconductor optical amplifier (RSOA)-based transmitter with 100 Gb/s capacity and application in access and metro networks. The layout of the 1 Tb/s transmitter is depicted in Fig. 1a. The InP monolithic chips that are integrated on the silica motherboard include a single 10-fold array of distributed-feedback lasers (DFBs) emitting on the 100 GHz ITU grid, and five “twin IQ-modulator” chips, each one comprising two parallel IQ-modulators (4 parallel MZIs) that can operate up to 50 Gbaud. The output ports of the DFB array, and the input/output ports of the five modulator chips are combined by means of silica waveguides on-chip, so as to provide 10 WDM OOK or DPSK