IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 2, MARCH/APRIL 2011 853 Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters Óscar Lucía, Student Member, IEEE, Isidro Urriza, Luis. A. Barragán, Denis Navarro, Óscar Jiménez, Student Member, IEEE, and José M. Burdío, Member, IEEE Abstract—This paper presents a hardware-in-the-loop (HIL) simulation technique applied to a series-resonant multiple-output inverter for new multi-inductor domestic induction heating platforms. The control of the topology is based on a system- on-programmable chip (SoPC) solution, which combines the MicroBlaze embedded soft-core processor and a customized pe- ripheral that generates the power converter control signals. The firmware is written in C, and the customized peripheral is de- scribed using a hardware description language. Simulating the whole system using digital or mixed-signal simulation tools is a very time-consuming task due to the embedded processor model complexity, and additionally, it does not support tracing C in- structions. To overcome these limitations, this paper proposes a real-time simulation test bench. The embedded processor core, peripherals, and the power converter model are all implemented into the same field-programmable gate array (FPGA). Using the hardware and software debugging tools supplied by the FPGA vendor, currents and voltages of the power converter model are monitored, and firmware C instructions are traced while running on the embedded processor core. Then, it is presented a design flow that is proven to be an effective and low-cost solution to verify the functionality of the customized peripheral and to implement a platform to perform firmware verification. Index Terms—Electromagnetic induction, field-programmable gate arrays (FPGAs), modeling, resonant inverters. I. I NTRODUCTION T HE IMPLEMENTATION of multiple-inductor power converters requires often the development of specific- purpose control architectures to obtain the most of the con- verter. These are usually based on a processor, which provides software (SW) flexibility, and specific-purpose hardware (HW), which provides customized functionalities. In addition, recent Manuscript received April 17, 2010; revised July 12, 2010 and September 16, 2010; accepted September 27, 2010. Date of publication December 30, 2010; date of current version March 18, 2011. Paper 2010-IPCC- 140.R2, presented at the 2010 IEEE Applied Power Electronics Conference and Exposition, Palm Springs, CA, February 21–25, and approved for publication in the IEEE TRANSACTIONS ON I NDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. This work was supported in part by the Spanish Ministerio de Educación y Ciencia under Project TEC2010-19207 and Project CSD2009-00046, in part by the Diputación General de Aragón under Project PI008/08, and in part by the Bosch and Siemens Home Appliances Group. The authors are with the Department of Electronic Engineering and Commu- nications and the Aragon Institute of Engineering Research (I3A), University of Zaragoza, 50018 Zaragoza, Spain (e-mail: olucia@unizar.es). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2010.2102997 trends suggest the integration of both functionalities in a single chip using an embedded processor, intellectual property (IP) cores, and some customized peripherals, providing a so-called system-on-programmable-chip (SoPC) solution [1]. The power converter and the embedded processor can be simulated using mixed-signal [2] and cosimulation [3] tools. Another approach is the holistic one, which proposes the use of a unique description language during the whole development procedure [4]. These approaches allow full visibility of internal signals. However, they do not allow tracing the C instruc- tions, and simulations are extremely slow due to the embedded processor cycle accurate model. Another approach is to con- nect the power converter to the field-programmable gate array (FPGA) and make real-time SW debugging of the embedded processor; however, the power converter can be damaged due to any malfunction of the SW algorithm. The utilization of FPGA embedded processors requires SW debugging in addition to HW verification tools. Some HW/SW coverification tools are available, such as Seamless FPGA form Mentor Graphics [5]. Another approach to speed up simulation and debug the SW system at HW speeds while eliminating the risk of damaging the actual power converter is the utilization of HW-in-the-loop (HIL) simulation [6]–[11]. HIL is based on adding at least one actual subsystem into the loop. Some works have been developed using an FPGA in the loop [3], [12]–[16] or using the commercially available dSPACE solution [9]. In [12], [13], the power converter model is im- plemented in fixed point on an FPGA, and the digital controller runs on an external DSP [3], [12] or CPU [13]. In [14], the FPGA is used as a high-speed peripheral input/output device. In [15], the controller is implemented in the FPGA, but the power converter model runs on a PC. In [16], the plant model and the power converter are implemented in fixed point into the same FPGA. However, none of these digital controllers use an FPGA embedded processor. The aim of this paper is to provide a design flow to obtain a real-time FPGA-based test bench to perform HW/SW verifi- cation for the proposed SoPC system. The design flow verifies the functionality of the customized peripherals and the power converter model without the need of simulating the embedded processor cycle accurate model. Thus, it accelerates simulation of the whole system, shortens the verification time, and allows SW development while avoiding the risk of damaging real prototypes. The main benefit of the proposed test bench is the 0093-9994/$26.00 © 2010 IEEE