17th Telecommunications forum TELFOR 2009 Serbia, Belgrade, November 24-26, 2009. Dual Dynamic Biasing with Input Power Pre- compensation for Class-A/AB enhancement Juan F. Miranda 1 , Student Member, IEEE, Walter Caharija 2 , Morten Olavsbråten 1 , Member, IEEE, and Karl M. Gjertsen 3 , Senior Member, IEEE 1 Norwegian University of Science and Technology (NTNU), 2 University of Trieste, 3 NERA Networks Abstract — A novel dynamic biasing methodology specially oriented towards high-efficiency class-A/AB design is presented. To achieve flexibility in the efficiency/linearity tradeoff, the gate and drain voltages as well as the input power are varied as a function of the desired output power. The aim is Power Added Efficiency (PAE) maximization restrained by linearity conditions. Simulation results for a 30dBm GaAs pHEMT amplifier yielded gain levels between 10.5 and 11dB for the whole power range, phase variation limited to 2.6° only. The PAE was found to be 25% in average over the dynamic range. This is three times as large as the static bias case. The second and third harmonic vary from -58dBc to -25dBc and -62dBc to -42dBc respectively hence preserving linear behavior. Keywords — Dynamic bias, envelope tracking (ET), smart biasing, high efficiency, class-A amplifiers, slice plots, contours. I. INTRODUCTION ODERN modulation formats have highly varying envelope signals in order to optimize the use of spectral resources. To avoid nonlinear distortion a high- linearity class-A amplifier is typically used at several dB of back-off, which has the side effect of dramatically decreasing efficiency [1]. The approach of smart bias variation in non-switching amplifiers goes back to Envelope Tracking (ET), where the principle was to continuously adjust the drain bias voltage of a class-B amplifier according to the envelope power of the input signal [1]. For the case of a class-A amplifier K. Yang et al. [2] showed that Power Added Efficiency (PAE) is nearly three times as much when gate and drain feeds are varied together continuously compared to the case when they are varied separately; and that PAE increases by a factor of 8 compared to a static bias case (i.e., constant supply voltages). A different approach to the bias variation problem was proposed in [3]. Pairs of input power and drain bias values (P in ,V DD ) are chosen so that for a given fundamental output power level (P out ) the DC power consumption is minimized. The same principle is used in [4] for Switching Mode amplifiers but considering also the output phase dependency on the input phase, input power and drain bias. By evaluating a path for maximum PAE and a path for constant phase for each P out level, it was shown that the bandwidth of the DC/DC converter and of the input to the amplifier was smaller for the constant phase path while PAE was still high. Figure 1. Simplified block diagram of the Dynamic Biasing system for class-A/AB amplifier enhancement. This work endeavors to establish a new design methodology for dynamically biased class-A/AB amplifiers; which studies the synchronized variation of gate and drain voltages together with the input power thus establishing a “dynamic bias path”. These three degrees of freedom will allow us to explore not only maximum PAE or constant output-phase variation paths [3, 4] but also many others that will be chosen according to specific design goals at the output (i.e., maximum output power, gain level and flatness and second and third harmonic power). Figure 1 shows a simplified diagram of the DB system. Note that the output power of the amplifier is set by the modulator which in a digital or analog fashion acts over the gate and drain controls, as well as the pre- compensation stage. Digital Pre-distortion (DPD) can be included in the pre-compensation stage (PCS) if desired. Mathematically, the goal is to run a 1-tone static characterization on the PA to determine 3 functions: V GG (P out ), V DD (P out ), P in (P out ) along the whole output power range. M 397