Leakage Current, Reliability Characteristics, and Boron Penetration of Ultra-Thin (32-36A) 02-Oxides and N2O/NO Oxynitrides zy Chuan Lin, Anthony I. Chou, Kiran Kumar, Prasenjit Chowdhury, and Jack C. Lee MicroelectronicsResearch Center, The University of Texas at Austin, Austin TX 78712 ‘Abstract In this paper, we investigate the effects of BF2- implantation into the Si substrates and boron penetration from P+ poly gate on initial oxide leakage current and reliability of ultra-thin gate oxides (02 and N20/NO oxynitrides with thickness of 32-36A). It is demonstrated that N20 growth is less susceptible to substrate conditions than 0 2 growth. Moreover, N20-oxides exhibit lower initial leakage current than 02-oxides, which is very important for low power applications. Introduction Different channel implant techniques and surface- channel PMOSFETs with P+ gate have been used successfully to suppress the short channel effects. However, the effects of these implants on ultra-thin oxide reliability have not been studied in detail, especially in the ultra-thin gate oxide regime (<40A). Implantation-induced substrate damages, which are not completely removed during annealing, inevitably can cause degradation of oxide reliability. This problem is aggravated in deep submicron CMOS processing because of the tight thermal budget control. On the other hand, diffusion of boron from P+ gate leads to poor threshold voltage control, increased subthreshold swing, and degraded oxide reliability [l-31. In this paper, we investigate the effects of ion implantation into the Si substrates and boron penetration from P+ poly gate on ultra-thin gate oxide (32-36A) reliability. Experiment Dual-gate CMOS test capacitors were fabricated using the process described in Table 1. BF2 was implanted through a zyxwvutsr l5OA sacrificial oxide into the Si substrates before gate oxidation for NMOS devices, while there was no substrate implantation for PMOS devices. The ultra-thin (32-36A) gate oxide was grown using rapid thermal processing (RTP) system in either an 0 2 or N20 ambient, followed by an NO anneal for some of these wafers. Poly deposition (3500A) was immediately performed after gate oxidation. P+ poly gate was implanted with BF2, while N+ poly gate was POCl3 doped. The active area of MOS capacitors is zyxwvutsrq 5 x loq5 cm-2. N20 growth was found to provide a better thickness uniformity than 0 2 growth, probably due to the reduced oxidation rate in a N20 ambient (Table 2). NMOS 02-oxides grown on BF2-implanted substrates show a degradation of oxide reliability (i.e., reduced charge- to-breakdown Qbd values) in comparison to the control (no implant) oxides (Fig. la), while there is no obvious degradation for thicker oxides zyxw (>70A) (Fig. lb). This shows that thin oxides are more susceptible to Si substrate defects than thicker oxides. It is believed that the incorporation of implant-inducedsubstrate damages into the oxide during gate oxidation process leads to the degradation of oxide reliability. In fact, oxide reliability (Qbd) improves with higher annealing temperatures. N2O-oxides grown on BF2- implanted substrates exhibit higher Qbd values and are even better than 02-oxides on non-implanted substrates. The devices with N20-oxide exhibit lower initial leakage current than those with 02-oxide [4] (Fig. 2). This was observed for both implanted and non-implanted substrate cases. The lower leakage current is believed to be due to the improved structural transition layer in N20-oxide [5,6] which plays a significant role in the ultra-thin oxide regime. It should be noted that for thicker oxide regime, N 2 0 and 0 2 oxides have the same initial oxide leakage behavior [5]. BF2-implant into the substrate inevitably causes higher initial leakage current (Fig. 3). High annealing temperature reduces the initial oxide leakage current. Note that this increase in oxide leakage current for substrate implant is usually not observed in thicker oxide (>70A) with high annealing temperatures. However, in ultra-thin oxide thickness regime (32-36&, structural transition layer becomes more critical; any additional defects would lead to reduced barrier heights and hence increased initial oxide leakage current. Stress induced leakage current (SILC) after stress fluence of +10C/cm2 was found to be higher for the substrate-implanted samples and 0 2 samples, compared to non-implanted and N 2 0 samples, respectively (Fig. 4). Even with an extended anneal ( zyx 1050°C 30 min.), an increase in S L C has been observed for substrate implanted samples. The dependencies of SILC current (Fig. 4) and charge trapping behavior (Fig. 5) on process variation are very ~n 13.4.1 0-7803-3393-4 $5.00 zyxwvutsrqp O 1996 IEEE IEDM 96-331