L. Svensson and J. Monteiro (Eds.): PATMOS 2008, LNCS 5349, pp. 399–408, 2009. © Springer-Verlag Berlin Heidelberg 2009 Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level Felipe Machado 1 , Teresa Riesgo 2 , and Yago Torroja 2 1 Departamento de Tecnología Electrónica, ESCET, Universidad Rey Juan Carlos c/ Tulipán s/n. 28933 Móstoles, Madrid, Spain 2 Centro de Electrónica Industrial, ETSII, Universidad Politécnica de Madrid c/ José Gutiérrez Abascal, 2. 28006 Madrid, Spain felipe.machado@urjc.es, {teresa.riesgo,yago.torroja}@upm.es Abstract. This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size. Keywords: Switching activity, CAD, RTL, BDD, activity estimation, digital circuit design, VHDL, circuit partition, power estimation. 1 Introduction During the last decades, the complexity of digital circuits has experimented an extraordinary growth. Besides, the scaling technologies have confronted digital designers with new challenges, such as power consumption and reliability. In addition to these difficulties, time-to-market pressures are aggravated by shorter product cycles due to the rapid technology changes. Therefore, new methodologies and tools are required to assist in digital circuit design. These methodologies and tools should facilitate a seamless design flow in which unnecessary design iterations are avoided. Frequently, despite the circuit functionality is correct, the non-fulfillment of other design issues impel to redesign it. The ability to estimate the final circuit characteristics constitutes an important aspect of a methodology. Estimators, which anticipate these final characteristics, help designers to make early design decisions and avoid costly design iterations. At the present time, power consumption is one of the most relevant issues to be considered in electronic design, both due to the proliferation of mobile devices and due to the excessive power consumption of high performance circuits, which require cooling