IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33, NO. 2, MAY 2010 389
Aligning Chips Face-to-Face for Dense
Capacitive and Optical Communication
John E. Cunningham, Ashok V. Krishnamoorthy, Ivan Shubin, Xuezhe Zheng, Senior Member, IEEE,
Mehdi Asghari, Dazeng Feng, and James G. Mitchell
Abstract—We report a new method that precisely self-aligns
face-to-face semiconductor chips or wafers to enable commu-
nication between the chips using electromagnetic waves. Our
alignment mechanism takes advantage of miniaturized versions
of two of nature’s idealized shapes: an inverse pyramidal shape
defined by a self-terminating wet-etch process in silicon and
micro-spheres with radii accurate to submicron accuracy. This
approach allows chips to be packaged using passive alignment
that is self locating and reaches nearly one micron level of chip
misalignment tolerance. Packages for applications to capacitive
and optical connections are presented. Additionally, we describe
a physical architecture for a multi-chip array packages with
“bridge” and “island” chips where the function of the bridge is
to transfer electromagnetic signals between island chips using
either capacitive or optical proximity communication. The bridge
chip can provide a predetermined amount of compliance to help
maintain alignment and thereby accommodate topology variants
in first level package or in chip thickness when required. Experi-
mental packages providing precise alignment between 1-D arrays
and 2-D arrays of chips are presented. We show that our precision
alignment mechanism enables high fidelity 10 Gb/s optical-prox-
imity-communication with reflecting mirrors micro-machined into
Silicon and co-integrated to low loss silicon-on-insulator waveg-
uides for chip-to-chip communication. The alignment mechanism
was also applied to a demonstration of chip-to-chip capacitive
proximity communication in a linear array of six chips. Alignment
measurements on a 4 4 array of chips are reported.
Index Terms—Communication systems, computer performance,
electromagnetic coupling, electromagnetic fields, mirrors, optical
communication, optical coupling, semiconductor devices, self-or-
ganizing control.
I. CAPACITIVE AND OPTICAL PROXIMITY COMMUNICATION
C
ONDUCTIVE electrical interconnections and on-chip
transceivers have long been used to provide reliable
interconnections between very-large-scale integration (VLSI)
electronic components, and have dominated the interconnect
Manuscript received October 19, 2008; revised July 28, 2009; accepted
September 24, 2009. First published February 25, 2010; current version
published May 05, 2010. This work was based upon work supported, in
part, by DARPA under Agreement HR0011-08-09-0001 and Agreement
W911NF-07-1-0529. This work was recommended for publication by Asso-
ciate Editor L. Zhang upon evaluation of the reviewers comments.
J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, and J. G.
Mitchell are with the Microelectronics Physical Sciences Center, Sun Microsys-
tems, San Diego, CA 92121 USA.
M. Asghari and D. Feng are with the Kotura Inc., Monterey Park, CA 91754
USA.
Color versions of one or more of the figures in this paper are available at
http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TADVP.2009.2037437
hierarchy for reasons of manufacturing cost, system packaging,
and ease-of-use. VLSI linewidths and on-chip clock speeds
have continued to scale, putting pressures on the ability of
traditional wires to achieve the off-chip bandwidths necessary
to fully and efficiently utilize the resources available on-chip.
When optimizing chip input and output circuits that communi-
cate conductively, electronic circuit and system architects must
design within the constraints of VLSI packages and circuit
boards by using advanced circuit techniques such as predistor-
tion, equalization, multilevel coding, and digitally controlled
feed-forward clock and data recover blocks—commonly
referred to as serializer-deserializer (SerDes) transceivers.
However, this generally increases the area and power consump-
tion and limits the maximum number of input/output (I/O)
circuits per chip. Current best-in-class SerDes transceivers [1]
are expected to yield signaling densities between 1–5 Tb/cm .
Proximity communication represents the general concept for
face-to-face integrated circuits communicating by capacitive
coupling [2] that we refer to as PxC. We extend this concept to
optical proximity communication or Optical Proximity Com-
munication (OPxC). In both cases, very high communication
signal density can be achieved when compared to wire-bonding
or solder-ball connections. In addition, to communicate
off-chip, the circuits need drive only a small, high-impedance,
capacitive pad (or optical modulator), much akin to the gate
of a transistor. In the capacitive case, the electrical pad pitch
may be on the order of 20 m. Each pad can drive signals at
line rates of 2.5–5 Gb/s or higher [3]. This provides a potential
communication density in excess of 1.25 Pb/cm . Experimental
capacitive proximity communication circuits have yielded areal
densities up to 43 Tb/cm to date [4]. Sun Microsystems has
built and tested capacitive PxC circuits in 180 nm CMOS and is
presently testing a 90 nm PxC test chip. In past prototypes we
have used capacitive pad pitches from 50 m down to 24 m.
Other academic research efforts have demonstrated pad pitches
as low as 9 m although without full packaging solutions [5].
Another group has demonstrated capacitive coupling between a
chip and the first level package using alignment based on solder
reflow [6]. At 24 m, PxC pads offer about a 50 areal density
improvement over traditional 150- m pitch chip I/O solder
bumps. In this comparison we consider short-reach SerDes,
which are links optimized for short traces within a package or a
very short board route; these SerDes consume much less power
compared to traditional memory or I/O links running over long
PCB traces [7].
In the optical proximity case, an optical coupler can be as
small as 20 m on a side. The optical coupler may communicate
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