WD4-1 zy I53 Asymmetric WDM All-Optical Packet Switched Routers Gerardo Castaiibn, Lubo Tancevski, Siva Yegnanarayanan, and Lakshman Tamil e-mail:Gerardo. C ast anon@ aud.alcat el .com. Alcatel Corporate Research Center, Richardson TX 75082. One of the major problems on the design of all-optical packet switching routers is to reduce the number of components and the number of components a signal has to traverse without affecting the teletraffic performance of a network. The number of components in a router is imposed by the degree of blocking probability desired. Blocking occurs when two or more competing packets at the input of a router desire the same output. Buffering, deflection routing, wavelength translation and link dimensioning [l] are some of the techniques that can be used to resolve the conflict of packets. The teletraffic performance and the optimization of the number of components in a router have been analyzed assuming an isolated node [2]. Usually an uniform distribution is assumed to assign the outlet destination to the incoming packets. The consequence of this kind of assumptions is that router architectures require a balanced wavelength conversion capability and also the same buffer depth per outlet. Therefore, due to this assumption the number of components used in the router increases. In this paper we show that due to the non-uniform network traffic behavior, routers require asymmetric wavelength conversion capabilities and also asymmetric buffering capacity to solve contention. This paper shows that due to the topology, packets may generate traffic bottlenecks produced by a tendency of the routing scheme to send packets with different destinations through preferred paths. This effect increases the traffic load and hence the probability of blocking at the output links of specific routers in the network and therefore a large buffer depth is required or an increment in the number of fibers per link. This paper shows that an integrated analyses by considering the network topology, routing scheme, dynamic traffic distribution and multiplexing gain of the routers into a single optimization model leads to an optimum all-optical router architecture and network design. The basic idea of integrated analyses is to simultaneously optimize decision variables of different functions that have traditionally been optimized in an isolated way. The router architectures shown in Fig. 1 are used in this analysis. Fig. l a [2] shows a symmetric router architecture, Fig. l b shows an asymmetric all-optical router with one shared output buffer. Fig. IC shows an asymmetric router with a wavelength conversion module with zyx C wavelength converters (WC). Fig. zyxwvutsr 2 shows comparison results of the number of optical tunable wavelength converters (OTWC) and the number of optical gates against the number of delay lines (NDL) of the three router schemes shown in Fig. 1. Observe that the number of optical gates required for architecture b is lower that architectures a and zyxwvu c. However architecture c requires less number of wavelength converters than a and b. The idea in architecture zyxw c is to optimize the number of WCs by considering that only about 30% of the WCs in architectures a and b are active (solving contentions of packets) per time slot as we will show. Since we are interested on the number of delay lines, the number of fibers per link required and the number of wavelength converters, we apply a router and network dimensioning algorithm which increases the buffer depth by one unit every time a packet is lost in a specific outlet. Also, in case the number of delay lines reaches the limit, we increase the number of fibers for that specific link. At the beginning of the simulation the buffer depth is 0 and the maximum buffer depth allowed during the network dimensioning period is 50. To obtain the number of WC required for architecture c we compute the maximum number of wavelength converters active during the steady state period of the simulation. The number of clock cycles (or time slots) used for the optical buffers dimensioning and for the transient period of the simulation are 200,000 which is enough for the network dimensioning and for the transient period to died out. To compute the statistics presented in this paper we collected data for 100,000 clock cycles during the steady state period. The traffic model for the injected self-similar traffic follows the conventional ON/OFF sources model where the traffic is represented by alternating ON (packet presence) and OFF (inter-arrival time) periods. The length T of each period is modeled according to the Pareto heavy-tail distribution zyxw T zyx = [l/(U)l/al, where U is a random variable uniform on [0,1] and indicates the ceil function. This implements