IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33,NO. 1,FEBRUARY 2010 285 The Impact of On-Wafer Calibration Method on the Measured Results of Coplanar Waveguide Circuits Qian Li and Kathleen L. Melde, Senior Member, IEEE Abstract—This paper compares four commonly used on-wafer calibration methods including multiline thru-reflect-line (TRL), line-reflect-reflect-match, line-reflect-match, and short-open-load- thru, for three diverse coplanar waveguide (CPW) circuits. The magnitudes and phases of and of the CPW circuits are compared to quantify how the specific calibration method influences measured scattering parameters. Special care is taken to ensure that the measured scattering parameters are normalized to the same reference impedance and reference plane for accurate comparison. The measured results are compared with full-wave simulations to provide additional assessment of accuracy. A method to de-embed the discontinuity of the CPW at the probe tip and the CPW of the test structures is presented. The effect of probe-to-device-under-test discontinuity is effectively modeled by one- or two- section of shunt capacitor and series inductor. The results show that the multiline TRL calibration method provides the highest transmission coefficient repeatability on not well-matched circuits and highest accuracy on the three circuits in this paper up to 40 GHz. Index Terms—Coplanar waveguide (CPW), high-frequency packaging, on-wafer measurements. I. INTRODUCTION T HE high-frequency performance of high-speed digital and wireless circuits has attracted increased attention. High-frequency modeling and simulation tools can be used to rapidly develop new circuit structures, yet the models must often be verified by comparison to broadband measurements. On-wafer measurements of coplanar waveguide (CPW) struc- tures are widely used since they can easily interface with probe stations. This eliminates the need for connectorized test structures. The important factors to consider include which calibration method to use, how to fabricate the necessary calibration artifacts, and the impact that the calibration method may have on the measurement results. The increase in clock speeds and the push to higher frequencies of operation mean that many of the calibration approaches typically used at lower frequencies must be reevaluated. The verification of accurate high-frequency design and analysis tools mean that the mea- sured results on the test structures must also be very accurate Manuscript received September 26, 2008; revised May 13, 2009. First pub- lished October 02, 2009; current version published February 26, 2010. This work was supported by the Semiconductor Research Corporation (SRC) under Task ID 1292.063. This work was recommended for publication by Associate Editor J. Tan upon evaluation of the reviewers comments. The authors are with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 USA (e-mail: melde@ece.arizona. edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2009.2025365 at increasingly higher frequencies. In this paper, we compare the differences in the results and the implementation of some commonly-used calibration methods. We assess the repeata- bility and compare the results of the measurements of several different types of CPW circuits to full-wave simulations. The calibrations are based on different error models and may have significant effects on the measurement accuracy and repeatability. Multiline thru-reflect-line TRL (ML-TRL), line-reflect-reflect-match (LRRM), line-reflect-match (LRM), and short-open-load-thru (SOLT) are popular on-wafer calibra- tion methods and are available in [1]. The ML-TRL calibration artifacts and the device-under-test (DUT) typically reside on the same substrate. This dramatically reduces errors due to differences of the substrate materials or CPW dimensions between the calibration standards and DUT. The standards used for LRRM, LRM, and SOLT are realized on a commer- cially-available impedance standard substrate (ISS). There may be differences between the CPW dimensions and materials of the ISS (for calibration) and the DUT (for measurement) that affect the measurement results at high frequency [2]. Previously reported calibration comparison techniques pri- marily focus on the error bound of the worst-case measure- ments [2], [3]. Some other comparison techniques [4] are based on measurements of different verification standards, such as open-stubs and a straight line standard. This paper presents a new approach that provides guidance and insight into the im- pact of calibrations on measured results. The impact of the cal- ibration method is applied to specific CPW circuit structures used by design engineers. The investigation includes a diverse set of CPW structures that include a straight transmission line, a stepped impedance line, and a bandpass filter. These struc- tures exhibit diverse responses, such as low reflection (for the line), and a narrow filter response. In this paper, the average and standard deviation of the measured -parameters are compared. This paper compares the impact of the measured results ob- tained from the different calibrations to full-wave simulations. The simulations are used to provide another assessment of mea- surement accuracy. The discussion is intended to be broad and to relate to engineers who must compare measured results with simulations. Some of the previous work on this subject have fo- cused primarily on the measurements and relate to those gen- erally familiar with the techniques and terminology. Before the comparisons are conducted, all of the scattering parameters are normalized so that the measured results are referenced to the same port impedance and reference plane. This is an important point to consider, since some calibrations approaches are refer- enced to a 50 termination and some are not. An accurate com- parison of accuracy and to simulated results requires that they all be normalized to the same reference impedance and plane. The 1521-3323/$26.00 © 2010 IEEE