IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003 1215 Analysis and Compact Behavioral Modeling of Nonlinear Distortion in Analog Communication Circuits Petr Dobrovolný, Member, IEEE, Gerd Vandersteen, Member, IEEE, Piet Wambacq, Member, IEEE, and Stéphane Donnay, Member, IEEE Abstract—The design of analog front-ends of digital telecom- munication transceivers requires mixed-signal simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency de- pendent. This paper describes an analysis and modeling method based on Volterra theory [1], [2]. The method derives bottom-up models of nonlinear analog continuous-time circuits. These behavioral models predict the dominant nonlinear effects using a composition of linear transfer functions and multiplications. This makes it possible to accurately model frequency dependencies and to gain insight into the dominant nonlinear sources of the circuit. The basic models are afterwards described using its mul- ticarrier complex low-pass representation to enable their efficient cosimulation with the digital circuits in a dataflow simulation environment.The multicarrier representation is a direct extension of the classically used complex low-pass equivalent models, which considers the modulation of a single carrier only. The accuracy of the multicarrier representation is higher than classical complex low-pass equivalent models since out-of-band nonlinear distortion is taken into account. The main advantage of the proposed technique is that it yields both insight in the nonlinear behavior at the circuit level and that it provides an important gain in simulation efficiency of RF integrated circuits at the system level. Both aspects are demonstrated on a 5-GHz WLAN design. Index Terms—Circuit, cosimulation, device models, modeling, simulation. I. INTRODUCTION T HE DESIGN of today’s digital wireless communication systems is driven by requirements for miniaturization, lower power consumption, and high flexibility. Meeting these demands means a serious challenge for the design of the analog front-ends in the transmitters and the receivers. The signal degradation caused by the analog front-ends (noise, nonlinear distortion, etc.) must be kept as low as possible. The total effect of signal degradations of the complete system, including both the analog and the digital part, can be quantified by means of the bit-error-rate (BER). A prediction of the BER requires lengthy simulations since a large number of symbols must be transmitted from the transmitter to the receiver. Therefore, it is very important that the inclusion of Manuscript received May 31, 2002; revised September 25, 2002 and March 15, 2003. This paper was recommended by Guest Editor H. A. Mantooth. The authors are with the Interuniversity MicroElectronics Center, B-3001 Leuven, Belgium (e-mail: Petr.Dobrovolny@imec.be). Digital Object Identifier 10.1109/TCAD.2003.816220 Fig. 1. Design flow for the analog front-ends that links the architectural, circuit, and layout levels of description. the RF front-end nonidealities in BER simulations do not slow down the computations too much. A cosimulation of the digital parts, described at a high abstraction level, with the analog parts described at the circuit-level, is, therefore, not feasible. The possible strategy of a mixed-signal design flow that covers various abstraction levels was suggested in [3]. The part of the mixed-signal flow, related to the analog front-end blocks, is shown in Fig. 1. The design flow starts with a high-level simulation of a front-end architecture. At this stage, analog–digital tradeoffs can be made. Afterwards, the architecture is split into analog and digital parts according to the chosen tradeoff. The digital parts are designed in a separate design flow (not shown in Fig. 1) [4]. The models for the analog blocks are very rough during these first high-level simulations. These simulations provide an initial set of specifications for the individual analog/RF circuits that are used as input for the circuit-level design. This circuit-level design can be performed in a manual way or by using analog synthesis tools [5]. After the circuit design, the layout can be generated. Again, CAD tools for analog placement and routing could be used here to speed up the process [6]. 0278-0070/03$17.00 © 2003 IEEE