3034 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 9, SEPTEMBER 2011 Two-Stage Degradation of p-Channel Poly-Si Thin-Film Transistors Under Dynamic Negative Bias Temperature Stress Jie Zhou, Mingxiang Wang, Senior Member, IEEE, and Man Wong, Senior Member, IEEE Abstract—Degradation of p-channel poly-Si thin-film transis- tors under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed under the dynamic NBT stress. Device threshold voltage (V th ) shifts toward positive values in the first stage to more negative values in the second stage. The capacitance–voltage characteristic indi- cates a negative-charge generation in the gate oxide during the dynamic NBT stress, which is responsible for the positive V th shift, while the well-known dc NBT instability effect causes the negative V th shift. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. A degradation mechanism is proposed to explain the negative-charge generation under the dynamic NBT stress. Index Terms—Dynamic effect, negative bias temperature (NBT) instability (NBTI), polycrystalline silicon (poly-Si) thin-film tran- sistors (TFTs). I. I NTRODUCTION D UE TO THEIR application in integrated active-matrix displays, poly-Si thin-film transistors (TFTs) have re- cently attracted research interest. Negative bias temperature (NBT) instability (NBTI) is found to be a key reliability issue in p-channel poly-Si TFTs [1]–[4], which causes a negative shift of device threshold voltage (V th ) under dc stress due to inter- face and/or grain boundary trap generation [1]–[4]. However, in circuit applications, devices are subject to dynamic operations. In p-MOSFETs, dynamic NBT-stress-induced degradation has been widely investigated [5]–[7]. A significant recovery of the NBTI degradation is observed after removal of stress voltage [5]–[7]. Nevertheless, there is still a lack of studies on the degra- dation of TFTs under dynamic NBT stress. Liao et al. reported that the degradation was similar to dc NBTI degradation [8]. Huang et al. reported that little degradation was observed under a dynamic NBT stress between −25 and 0 V [9]. However, recently, we have reported a two-stage degradation behavior of Manuscript received January 28, 2011; revised May 21, 2011; accepted May 28, 2011. Date of publication June 27, 2011; date of current version August 24, 2011. This work was supported in part by the Natural Science Foundation of Jiangsu Province of China under Grant BK2009112, by the National Natural Science Foundation of China under Grant 61076085, and by the State Key Laboratory of ASIC and System, Fudan University, under Grant 10KF002. The review of this paper was arranged by Editor B. Kaczer. J. Zhou and M. Wang are with the Department of Microelectronics, Soochow University, Suzhou 215006, China (e-mail: Mingxiang_wang@suda.edu.cn). M. Wong is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2158582 poly-Si TFTs under dynamic NBT stress [10]. V th shifts toward positive values in the first stage to more negative values in the second stage. In this paper, such phenomenon is investigated systematically and is attributed to a new dynamic mechanism combined with conventional dc NBTI effect. The dynamic effect is related to the pulse falling edge and is enhanced when the falling time is shorter and/or the amplitude is higher. The capacitance–voltage (C–V ) characteristic indicates significant negative-charge generation in the gate oxide during the dy- namic NBT stress. A new mechanism is tentatively proposed to explain the charge generation by considering the role of OH − . II. EXPERIMENTS The poly-Si TFTs used in this study were in conventional self-aligned top-gated structure. Four-inch silicon wafers cov- ered with 500-nm thermal oxide were used as starting sub- strates. A 50-nm amorphous-Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550 ◦ C. Wafers were immersed in a 10-ppm nickel nitrate solution, followed by a 6-h anneal at 590 ◦ C in N 2 ambient. Af- ter PSG gettering, the samples were preannealed at 630 ◦ C for 8 h in a furnace. After defining the active islands, a 100-nm LPCVD low-temperature oxide layer was deposited at 425 ◦ C as gate insulator, and a 280-nm LPCVD a-Si layer was deposited as gate material, which was later crystallized by nickel-induced crystallization (MIC). After gate patterning, a self-aligned boron implantation with a dose of 4 × 10 15 cm −2 was introduced to form the source and drain. Dopant activation and gate MIC were done simultaneously by a 6-h anneal at 630 ◦ C in N 2 ambient. Contact holes were opened, and a 500-nm-Al–1%Si layer was then sputtered and patterned as metal pads. Finally, wafers were sintered in forming gas at 420 ◦ C for 30 min [11]. The device channel length (L) varies from 2 to 30 μm, while the channel width (W ) is fixed at 10 μm. Negative gate pulse stress is applied to TFTs with the source and drain grounded. A pulse waveform is shown in Fig. 1, where V gb /V gp , t r /t f , and t gb /t gp stand for the pulse base/peak voltages, pulse rising/falling times, and pulse durations of base/peak voltages, respectively. V gb is fixed at zero for all stresses. The pulse is applied by Agilent 4156C with pulse generator Agilent 41501B. Voltage pulses are monitored by Agilent 54622D oscilloscope. Overshoot is only found in the gate terminal, which is ≤ 5 V for the highest pulse amplitude (−40 V) and shortest transition edge (0.1 μs). Thus, undesirable 0018-9383/$26.00 © 2011 IEEE