IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 2, FEBRUARY 2007 225 Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses Min Xue, Mingxiang Wang, Zhen Zhu, Dongli Zhang, and Man Wong, Senior Member, IEEE Abstract—Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin- film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V d-stress and in high V d-stress condition. Defect generation distribution along the channel appears to be dif- ferent in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress. Index Terms—Hot-carrier (HC) degradation, low-temperature polycrystalline silicon (LTPS), metal-induced lateral crystal- lization, reliability, self-heating (SH) degradation, thin-film transistors (TFTs). I. INTRODUCTION L OW-TEMPERATURE polycrystalline silicon (LTPS) thin-film transistors (TFTs) are fabricated with the max- imum process temperature lower than 600 ◦ C, enabling the utilization of cheap glass substrates. High performance and reliable LTPS TFT technologies are highly desirable to meet the demands of system on panel applications such as monolithically integrated flat panel displays [1], [2]. While extensive investiga- tions have been done in excimer laser crystallized (ELC) poly- Si technology, a recently developed approach, metal-induced laterally crystallized (MILC) poly-Si technology is drawing increasing attention. It has been demonstrated as a promising technology for system on panel applications with much reduced Manuscript received March 31, 2006; revised September 22, 2006. This work was supported by the National Natural Science Foundation of China, under Contract 60406001. The work of D. Zhang and M. Wong was supported by the Research Grants Council of the Hong Kong Special Administrative Region. The review of this paper was arranged by Editor G. Groeseneken. M. Xue, M. Wang, and Z. Zhu are with the Department of Microelectron- ics, Soochow University, Suzhou 215021, China (e-mail: mingxiang_wang@ suda.edu.cn). D. Zhang and M. Wong are with the Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Kowloon, Hong Kong. Digital Object Identifier 10.1109/TED.2006.888723 manufacturing cost compared with ELC technology [2]–[4]. However, before any practical application of LTPS TFTs can be implemented, TFT device reliability is an important issue that needs to be improved. Up to now, almost no detailed work was reported on the device reliability of MILC TFTs. This is in contrast to those systematic investigations that have been done on the reliability of ELC poly-Si TFTs [5]–[14]. As a primary step to understand reliability of MILC TFTs, device degradation behavior and degradation mecha- nism should be investigated. In this paper, device degradation behaviors of typical n-type MILC TFTs under dc bias stress have been studied. Bias conditions are identified for two typical degradation mechanisms, i.e., hot-carrier (HC) stress [5]–[7], [11]–[18] and self-heating (SH) stress [6], [8]–[10], [14]. Dependence of device degradation on stress condition has been investigated. Different degradation behaviors under HC stress and under SH stress have been observed and compared. Degradation behaviors of normal and of reverse condition are compared for both HC and SH stress conditions. A unified degradation model is tentatively proposed to understand our experimental observations. II. EXPERIMENTS Typical top gated unilaterally crystallized MILC poly-Si TFTs are used in this paper. The fabrication procedure is as the following. First, 1200-Å-thick amorphous-Si was deposited using LPCVD at 550 ◦ C on an oxidized silicon wafer. Then, ac- tive islands were patterned and 1000-Å low-temperature oxide was deposited by LPCVD at 420 ◦ C as gate oxide, followed by deposition of 3000-Å amorphous-Si also by LPCVD at 550 ◦ C as gate material. After gate patterning, Ni induce windows were opened and 5-nm-thick Ni was deposited. The gate MIC and channel MILC were simultaneously done at 550 ◦ C for 16 h. Dopant was introduced by self-align phosphorous implantation with a dose of 4 × 10 15 cm -2 and was activated at 550 ◦ C for 8 h. 5000-Å LTO was deposited as isolation layer and contact holes were opened. Then, 5000-Å Al-1% Si layer was deposited and patterned into electrodes. The devices were finally passivated by a 5000-Å-thick PECVD oxide at 300 ◦ C. MILC poly-Si TFTs with W/L = 10/10 μm are used for stress test and measured by using Agilent 4156C semicon- ductor parameter analyzer and Vector MX-1100B prober. Devices are characterized both in the normal and in the reverse modes. In the reverse mode, device source and drain electrodes 0018-9383/$25.00 © 2007 IEEE