An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors Meng Zhang, Mingxiang Wang * Department of Microelectronics, Soochow University, Suzhou 215006, PR China article info Article history: Received 1 December 2009 Received in revised form 31 December 2009 Available online 9 February 2010 abstract Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse fall- ing time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed. Crown Copyright Ó 2010 Published by Elsevier Ltd. All rights reserved. 1. Introduction Low temperature polycrystalline silicon (LTPS) thin film transis- tors (TFTs) have attracted much attention for integrated active ma- trix displays due to their higher mobility. TFTs in driver circuits, unlike those in the pixels, are subjected to high frequency voltage pulses. Such application would require devices to withstand dy- namic stress on both gate and drain electrodes [1]. Therefore, re- lated dynamic degradation phenomena should be carefully examined. Most previous dynamic degradation studies focused on device instability under gate pulse stress with the drain elec- trode either grounded [2,3] or DC biased [4,5], where the degrada- tion was controlled by a dynamic hot carrier (HC) effect related to pulse transition time [2–5]. Others focused on device reliability un- der synchronized gate and drain pulses, where AC self-heating (SH) effect [6] or combined AC SH and HC effect [7] was involved. How- ever, dynamic device degradation under drain pulse stress has not been reported yet. In this work, degradation behaviors of n-type LTPS TFTs under drain pulse stress is first studied at various pulse parameters such as amplitude, frequency (f) and transition time. It is found that a dynamic HC effect dominates the device degradation. Such degra- dation strongly depends on pulse rising time (t r ) but is indepen- dent of falling time (t f ). Based on experimental and simulation results, a PN junction degradation mechanism considering carrier emission and trapping is discussed. As a comparison, the same stress test is also performed on high temperature polycrystalline silicon (HTPS) TFTs. The observation is consistent with the pro- posed degradation mechanism. 2. Experimental TFTs used in this study were in conventional self-aligned top- gate structure. First, a 50 nm amorphous-Si (a-Si) was deposited on an oxidized silicon wafer by low-pressure chemical vapor depo- sition (LPCVD). After patterning of a-Si active islands and LPCVD of an 80 nm low temperature oxide (LTO), crystallization inducing window was opened through the LTO and 5 nm Ni was evaporated by electron beam at room temperature. The wafers were subse- quently annealed for metal-induced unilateral crystallization of ac- tive islands at 550 °C for 24h in N 2 ambient. After Ni removal, another extended anneal was done at 550 °C for 72 h. Then LTO was removed and another 100 nm LTO layer was deposited as gate oxide, followed by LPCVD of 300 nm poly-Si as gate. After gate pat- terning, a self-aligned phosphorous implantation with a dose of 4 Â 10 15 cm À2 was done to form the source and drain, and subse- quently activated at 620 °C for 3 h. Contact holes were then opened before aluminum layer sputtering and patterning. Finally, wafers were sintered in Forming gas. For HTPS TFTs, 100 nm active layer was formed by solution based metal-induced crystallization of a-Si film at 550 °C for 3 h. Later it is recrystallized at 900 °C for 1 h in N 2 . by poly-Si oxidation at 950 °C for 48 min in dry O 2 . n-type LTPS TFTs subjected to the drain pulse stress have a de- vice width (W) 10À15 lm and length (L) 10 lm. Shown in Fig. 1 is the pulse waveform applied to the drain electrode. The pulse swings from zero to a high voltage level (V dh ) at a fixed pulse duty ratio of 50%. Stress parameters are pulse amplitude, f, t r and t f . For comparison, degradation of HTPS TFTs under the same stress con- dition is also examined. Devices are measured before and after 0026-2714/$ - see front matter Crown Copyright Ó 2010 Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.01.024 * Corresponding author. Address: Department of Microelectronics, Soochow University, PO Box 125, No.1 Shizi Street, Suzhou 215006, PR China. Fax: +86 512 6787 1211. E-mail address: Mingxiang_wang@suda.edu.cn (M. Wang). Microelectronics Reliability 50 (2010) 713–716 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel