3276 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 12, DECEMBER 2007 Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Huaisheng Wang, Mingxiang Wang, Member,IEEE, Zhenyu Yang, Han Hao, and Man Wong, Senior Member, IEEE Abstract—Self-heating degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under various stress powers. A two-stage degradation behavior with turnaround effect at the initial stage is characterized. The initial degradation stage is re- lated to breaking of weak Si–H bonds. The floating-body effect by released hydrogen ions is responsible for the observed back- shift of the transfer curve during the initial stress. On the other hand, the normal degradation stage occurs by breaking of strong Si–Si bonds and trap generation at grain boundaries (GBs) and the gate oxide/channel interface. Our model is supported by observed different activation energies related to two degradation stages and a direct observation of the continuous increase in GB trap density during the normal degradation. Furthermore, during the normal degradation stage, an anomalous continuous field-effect mobility increase along with its V g dependence shift is first observed. It is clarified that this behavior is not a true channel mobility increase, but a consequence of stress-related trap generation. Index Terms—Field-effect mobility, metal-induced lateral crys- tallization, polycrystalline silicon (poly-Si), self-heating (SH) deg- radation, thin-film transistors (TFTs). I. INTRODUCTION L OW-TEMPERATURE polysilicon (LTPS) thin-film tran- sistors (TFTs) have attracted much attention for their po- tential for system-on-panel applications such as full integrated active matrix displays by liquid crystal or by organic light emit- ting diodes [1]. Although excimer laser crystallization (ELC) is currently a widely employed LTPS technology [2]–[5], recently, metal-induced lateral crystallization (MILC) has been demonstrated as a promising LTPS technology with some unique advantages over other techniques [6]. Currently, high- performance polycrystalline silicon (poly-Si) TFTs have been fabricated by using various technologies [6], [7]. However, device reliability still remains a limiting factor for poly-Si TFTs toward future application in large-scale integration circuits. It is Manuscript received August 13, 2007; revised September 14, 2007. This work was supported by the National Natural Science Foundation of China under Contract 60406001 and in part by the Research Grants Council of the Hong Kong Special Administrative Region. The review of this paper was arranged by Editor J. Suehle. H. Wang, M. Wang, Z. Yang, and H. Hao are with the Department of Microelectronics, Soochow University, Suzhou 215021, China (e-mail: Mingxiang_wang@suda.edu.cn). M. Wong is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.908907 particularly true for MILC TFTs since, up to now, there are still rarely reported studies on their device reliability [8], [9]. It has been identified for poly-Si TFTs that hot carrier (HC) stress [4], [5], [9]–[14] and self-heating (SH) stress [4], [7], [9], [14]–[18] are two key mechanisms inducing device degradation. In this paper, time-dependent SH degradation be- haviors of n-type MILC TFTs under different stress powers were systematically investigated. Channel temperature rise in stressed devices was simulated by the finite-element method. Two features in device degradation that are different from those previously observed for ELC TFTs, namely, two-stage degradation with a turnaround effect and anomalous field-effect mobility degradation, were observed. A unified model was proposed to understand the observed degradation behaviors. II. EXPERIMENTS TFTs used in this study were in conventional self-aligned top-gate structure. First, a 50-nm amorphous Si (a-Si) was deposited on an oxidized silicon wafer by low-pressure chem- ical vapor deposition (LPCVD). After patterning of a-Si active islands and LPCVD of an 80-nm low-temperature oxide (LTO), a crystallization-inducing window was opened through the LTO, and 5-nm Ni was evaporated by electron beam at room temperature. The wafers were subsequently annealed for metal- induced unilateral crystallization of active islands at 550 ◦ C for 24 h in N 2 ambient. After Ni removal, another extended anneal was done at 550 ◦ C for 24 h. Then, LTO was removed, and another 100-nm LTO layer was deposited as gate oxide, followed by LPCVD of 300-nm poly-Si as gate. After gate patterning, a self-aligned phosphorous implantation with a dose of 4 × 10 15 cm -2 was introduced to form source and drain, and subsequently activated at 620 ◦ C for 3 h. Contact holes were then opened before aluminum layer sputtering and patterning. Finally, wafers were sintered in forming gas. MILC TFTs with gate width/length W/L = 10/6 μm are stressed and characterized before and after stress by using Agilent 4156C semiconductor parameter analyzer and Vector MX-1100B prober. From transfer curves measured at V ds = 0.1 V, device characteristics such as threshold voltage V th , on current I on , field-effect mobility μ FE , and subthreshold slope SS are extracted. I on is defined at a gate voltage V g = 12 V. V th is determined by linear extrapolation of I d to zero. The uncertainty of V th extraction is within 0.2 V. Devices are characterized both in the normal and reverse modes. In the reverse mode, device source and drain electrodes are reversely 0018-9383/$25.00 © 2007 IEEE