IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001 1655 Characterization of an Individual Grain Boundary in Metal-Induced Laterally Crystallized Polycrystalline Silicon Thin-Film Devices Mingxiang Wang and Man Wong Abstract—A distinct grain boundary (GB) is formed when two crystallization fronts collide in metal-induced laterally crystallized (MILC) polycrystalline silicon (poly-Si) thin films. This has been used to study carrier transport across a single dominant GB. The average number of traps per unit area is found to be about /cm in this GB, significantly higher than that associated with the regular GBs in the bulk of MILC poly-Si. Though this single GB occupies a negligible fraction of the total device volume, it has been found to significantly affect both the resistance of MILC resistors and the leakage current of MILC thin-film transistors. Index Terms—Grain boundary, lateral crystallization, nickel, polycrystalline silicon, thin-film transistor. I. INTRODUCTION G RAIN boundaries (GBs) and their trap states significantly affect the performance of polycrystalline silicon (poly-Si) thin-film devices. In conventional poly-Si resistors, thermionic emission over the GB potential barrier is commonly proposed to be the dominant carrier transport mechanism [1]–[3], thus explaining the large reduction in electrical conductivity and the difficulty in resistivity control compared to their single-crystal counterparts at moderate doping concentrations. Furthermore, GB traps also profoundly affect the performance of poly-Si thin-film transistors (TFTs), leading to higher off-state leakage current, higher threshold voltage and degraded sub-threshold slopes [4], etc. Poly-Si has been formed using a variety of techniques, such as direct growth by low-pressure chemical vapor depo- sition (LPCVD) or annealing of amorphous silicon (a-Si) by solid-phase/laser crystallization (SPC/LC) [4]. Recently, nickel (Ni) based metal-induced lateral crystallization (MILC) of a-Si has been applied [5] to obtain high quality poly-Si thin films and high performance TFTs. This technique is both practical and promising because unlike LC, it is a low-cost batch process and unlike SPC, better quality poly-Si can be obtained. In the active islands of some MILC devices, distinct GBs (dubbed LLGBs [6]) transverse to the direction of current flow are formed by the collisions of MILC fronts advancing in oppo- site directions [5]–[7]. Different from the randomly distributed GBs in LPCVD, SPC and LC poly-Si, the location of the LLGB Manuscript received September 12, 2000; revised March 1, 2001. This work was supported by a grant from the Research Grants Council of Hong Kong. The review of this paper was arranged by Editor J. Vasi. The authors are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail: eemwong@ee.ust.hk). Publisher Item Identifier S 0018-9383(01)05691-X. in an MILC poly-Si island can be precisely controlled [5], [6], [8]. Consequently, if the LLGBs have measurable effects on electrical conduction in MILC poly-Si, they can be exploited as ideal test vehicles for GB transport models in poly-Si. In this work, the effects of the LLGBs on the characteristics of MILC poly-Si devices are studied by comparing the conduction behavior of MILC devices with or without the LLGBs. It will be shown that the resistance of MILC resistors can be signifi- cantly affected by the presence of the LLGBs, particularly for those with short lateral dimensions. Carrier transport across the LLGBs has been studied by extracting the resistance of an indi- vidual LLGB and measuring its temperature dependence. Mea- sured in terms of the density of trap states, the LLGBs have been found to be significantly more defective than the regular GBs in bulk MILC poly-Si. Furthermore, it has been observed that even in an MILC TFT with a channel length long enough such that the LLGB is located far away from the metallurgical junctions and their associated lateral electric fields, a considerable increase in off-state leakage current is still obtained. This is explained by the diffusion of the excess carriers thermally generated via the LLGB trap states. II. DEVICE FABRICATION Resistor fabrication began with the formation of 100 nm of a-Si on starting substrates of 100 mm, thermally oxidized (100)-oriented Si wafers using low-pressure pyrolysis of silane at 550 C. After the patterning of the a-Si active islands and the LPCVD of a 100 nm thick low-temperature oxide (LTO), 45 keV boron ions at a dose of /cm were implanted through the LTO. Small window openings overlapping the a-Si islands were made on selected areas of the LTO layer and 5 nm Ni was deposited by electron-beam evaporation at room temperature. The wafers were subsequently heat-treated at 530 C in a nitrogen (N ) ambient until complete MILC of the islands. The Ni windows on the islands are located in such a way that the a-Si regions between the electrical contacts are either metal-induced bilaterally crystallized (MIBC) or metal-induced unilaterally crystallized (MIUC), with the length of the MIBC resistor being twice that of the corresponding MIUC resistor (Fig. 1). It should be noted that an LLGB was deliberately and precisely formed at the center of each MIBC resistor. After the removal of any unreacted Ni, new windows (Fig. 1) for heavy implant were opened in photoresist on the islands to define the contact regions and the physical dimensions of the 0018–9383/01$10.00 © 2001 IEEE