Yield Factors Parametric Lithography- based Defect Density 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.35 micron 0.25 micron 0.18 micron 0.13 micron 0.09 micron Process Technology Nominal Yields Defect Density Lithography-based Parametric Yield Yield-Aware Cache Architectures Serkan Ozdemir Debjit Sinha * Gokhan Memik Jonathan Adams Hai Zhou EECS Department, Northwestern University {soz463, debjit, memik, jra760, haizhou}@ece.northwestern.edu Abstract One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields have dropped to around 50% or less. This figure is expected to decrease even further in future technologies. To attack this growing problem, we develop four yield-aware microarchitecture schemes for data caches. The first one is called Yield-Aware Power-Down (YAPD). YAPD turns off cache ways that cause delay violation and/or have excessive leakage. We also modify this approach to achieve better yields. This new method is called Horizontal YAPD (H- YAPD), which turns off horizontal regions of the cache instead of ways. A third approach targets delay violation in data caches. Particularly, we develop a VAriable-latency Cache Architecture (VACA). VACA allows different load accesses to be completed with varying latencies. This is enabled by augmenting the functional units with special buffers that allow the dependants of a load operation to stall for a cycle if the load operation is delayed. As a result, if some accesses take longer than the predefined number of cycles, the execution can still be performed correctly, albeit with some performance degradation. A fourth scheme we devise is called a Hybrid mechanism, which combines the YAPD and the VACA. As a result of these schemes, chips that may be tossed away due to parametric yield loss can be saved. Experimental results demonstrate that the yield losses can be reduced by 68.1% and 72.4% with YAPD and H- YAPD schemes and by 33.3% and 81.1% with VACA and Hybrid mechanisms, respectively, improving the overall yield to as much as 97.0%. 1. Introduction Decreasing yields in modern VLSI chip manufacturing is a critical issue faced by the semiconductor industry. In a drive to continue to meet the demands of Moore’s Law, process technology has continually transitioned to smaller sizes with current average feature sizes being as small as 65 nanometers. Although this scaling trend facilitates more gates, and therefore more performance and functionality to be packed onto every chip produced, it has made the manufacturability of these chips increasingly difficult [24, 39]. With process technologies scaling from 350 nanometers to 90 nanometers, chip yields have dropped from over 90% to just above 50% [18]. A recent study on 45 nanometer technologies reports yields around 30% [3]. This trend is depicted in Figure 1, which shows the expected yield for different manufacturing technologies and the factors on which the yield loss is attributed to. Factors limiting chip yields can be grouped into three categories: defect-density related yield loss, lithography based yield loss, and parametric yield loss. Defect-density related problems are caused by actual errors with the silicon, such as when a contaminating particle is introduced during fabrication. These are well-controlled as silicon and clean- room technology becomes more efficient. Lithography based failures occur when there are defects on the masks used to burn the silicon. These are tied to reticle patterns and are controlled as process technologies mature. Parametric yield loss, on the other hand, occurs because the manufactured chip does not meet a design parameter. For example, a microprocessor, which does not meet a frequency constraint or consumes too much power, may be tossed away. Figure 1. Yield factors for different process technologies [18] As shown in Figure 1, the impact of all the above factors has worsened with technology scaling. However, parametric losses are the largest inhibitor to chip yields [18] and contribute significantly to overall yield losses starting from the 0.18 micrometer technology generation [1, 10, 16, 24, 25]. For sub-180nm technologies, it becomes harder to control variations in device parameters such as channel length, gate width, oxide thickness, and device threshold voltage. Even in a mature technology like 130nm, these variations are known to cause a 30% variation in maximum allowable frequency of operation, and a fivefold increase in leakage power [10]. For newer technologies, these variations can be even higher: 20X increases in leakage have been * Debjit Sinha is currently with IBM Microelectronics, USA