ARTICLES PUBLISHED ONLINE: 10 JULY 2011 | DOI: 10.1038/NMAT3070 A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta 2 O 5-x /TaO 2-x bilayer structures Myoung-Jae Lee 1 * , Chang Bum Lee 1 , Dongsoo Lee 1 , Seung Ryul Lee 1 , Man Chang 1 , Ji Hyun Hur 1 , Young-Bae Kim 1 , Chang-Jung Kim 1 * , David H. Seo 1 , Sunae Seo 2 , U-In Chung 1 , In-Kyeong Yoo 1 and Kinam Kim 3 Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO x -based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10 12 . Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays. E ven to this day, 50 years since the development of Si-based memory technology, silicon complementary metal–oxide semiconductor devices dominate the memory industry 1–5 . The reason for flash memory’s dominance has been several advantages of Si charge-based memories over its counterparts such as phase-change random access memory (PRAM) 1 , ferroelectric RAM (FERAM) 2 and magnetoresistive RAM (MRAM) 3 . The basic requirements for a next-generation non-volatile memory begin with scalability, which allows for cost-effective research and processing, as well as opening viability in new fields such as media storage, traditionally the domain of optical disks or magnetic hard disks 6 . For a memory to be scalable down to nanoscale sizes two important factors must be realized. First, the switching current must scale down to the 10–100 μA region. Second, the switching mechanism must scale down at least to below the 10–30 nm technology node. PRAM has yet to succeed in the former category 3 , whereas MRAM and FERAM both have problems with the latter 2,3 . Other new memories, including the previously reported resistance-change memory (RRAM) 5,7–11 and the related memristor 12–14 , have also been lacking in these requirements. Furthermore, secondary but also important requirements of cycling endurance, data retention and switching speed should also be sufficient for robust commercial memory products. So far not even flash memory has been able to fulfil every one of the secondary requirements, especially the issue of speed, leading to programming times of up to microseconds. Once the secondary requirements have been exceeded, a truly universal memory, that is, the combination of working and storage memory, can be achieved. 1 Semiconductor Device Laboratory, Samsung Advanced Institute of Technology, Samsung Electronics, Yongin, Gyeonggi-do 446-712, Korea, 2 Department of Physics, Sejong University, Seoul 143-747, Korea, 3 Samsung Advanced Institute of Technology, Samsung Electronics, Yongin, Gyeonggi-do 446-712, Korea. *e-mail: myoungjae.lee@samsung.com; cj2.kim@samsung.com. These days, to overcome lithographic limits, three-dimensional stacking is also being explored. A passive array of crossbars yields the highest density for stacked structures. A passive two- terminal structure such as one diode–one resistor is considered advantageous over active structures that include a transistor. However, material considerations must be made in both metal and non-metal components. For example, any material that requires high processing temperatures will not be a suitable candidate for three-dimensional technologies owing to the low thermal budget. In general, oxide-based memories do not need any annealing or high-temperature deposition 5,15–17 and thus are considered to be the best option for stacked devices. It should also be noted that two-terminal designs are generally easily stackable. We report here on an asymmetric tantalum oxide-based RRAM that shows massive improvements in every memory specification over what has been previously reported 5,8,9,11,16,18 . Furthermore, we offer an optimized solution to the crossbar stray-leakage issue by using an antiserially connected stacked device structure with an intrinsic Schottky contact. We were able to demonstrate a working two-terminal device as first proposed in ref. 19 that eliminates the need for either a diode or transistor switch in a crossbar structure, while also eliminating the fringe cases requiring an external resistor for device operation. Devices were fabricated on bottom Pt lines as needed for crossbar structure devices. Next we deposited the TaO 2−x base layer using reactive sputtering of a Ta metal target in an oxygen and argon gas mixture. In contrast to previous metal–insulator– metal structures, we then used oxygen plasma to form a few- nanometre-thick nearly stoichiometric Ta 2 O 5−x layer. This process NATURE MATERIALS | VOL 10 | AUGUST 2011 | www.nature.com/naturematerials 625 © 2011 Macmillan Publishers Limited. All rights reserved