IEEE Proof Web Version IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010 1 High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique Mohamed El-Nozahi, Student Member, IEEE, Ahmed Amer, Student Member, IEEE, Joselyn Torres, Student Member, IEEE, Kamran Entesari, Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE Abstract—A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain–bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 m CMOS technology and achieves a PSR better than 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz. Index Terms—CMOS, DC-DC converters, feed-forward ripple cancellation, low drop-out regulator, power-supply rejection. I. INTRODUCTION T HERE is a great interest in efficient power management ICs. An important building block in power management is the low drop-out (LDO) linear regulator which often fol- lows a DC-DC switching converter, as shown in Fig. 1. It is used to regulate the supplies ripples to provide a clean voltage source for the noise-sensitive analog/RF blocks. Designing a stable LDO for a wide range of load conditions, while achieving high power-supply rejection (PSR), low drop-out voltage, and low quiescent current, is the main target using state-of-the-art CMOS technologies [1]–[4]. Recently, there has been an increasing demand to integrate the whole power management system into a single system-on-chip (SoC) solution. Hence, operating frequencies of switching con- verters are increasing to allow higher level of integration [5]. This trend increases the frequency of output ripples and there- fore the subsequent LDO regulator should provide high PSR up to switching frequencies. Conventional LDOs have poor PSR at high frequencies (above 300 kHz) especially the ones imple- mented using sub-250 nm technologies. The main reasons for Manuscript received June 03, 2009; revised December 09, 2009. Current ver- sion published February 24, 2010. This paper was approved by Associate Editor Philip Mok. This work was supported in part by Texas Instruments Inc. The authors are with the Department of Electrical and Computer Engi- neering, Texas A&M University, College Station, TX 77843 USA (e-mail: melnozahi@ieee.org; ahmed.amer@ieee.org; jotorres@tamu.edu; ken- tesar@ece.tamu.edu; e.sanchez@ieee.org; sanchez@ece.tamu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2009.2039685 Fig. 1. Block diagram of typical power management system. poor PSR are summarized as follows: 1) Finite output conduc- tance of the pass transistor, 2) low DC gain of sub-250 nm tech- nologies which requires complex gain stages to achieve better regulation, and 3) finite bandwidth of the feedback path. Researchers have contributed to improve power-supply rejec- tion techniques. Some of those techniques are: i) Using simple RC filtering at the output of the LDO [6]; ii) Cascading two reg- ulators [6]; iii) Cascading another transistor with the pMOS pass transistor along with RC filtering, using special technologies such as drain-extended FET devices, and/or charge-pump tech- niques to bias the gate of one of the transistors [7]–[9]. Simple RC filtering reduces the voltage ripple at the input of the LDO. However, this technique increases the drop-out voltage in LDO regulators that supply high current due to the high voltage drop across the resistance. Using an nMOS or pMOS transistor to cascade with the pMOS pass transistor can achieve high power- supply rejection over a wide frequency range. This technique in- creases the area and leads to a high drop-out voltage [7]. Charge pump techniques increase complexity and lead to higher power consumption because a clock is necessary along with RC fil- tering to remove clock ripples [9]. In summary, the main idea behind all previously proposed techniques is to provide more isolation between the input and output along the high-current signal path. Hence, the area consumption and drop-out voltage are large, which is not suitable for low-voltage technologies. In addition, these techniques provide high PSR at low frequencies, but are unable to provide sufficient PSR (better than 50 dB) at frequencies up to several MHz. To overcome the drawbacks of previously reported PSR LDO regulators, we introduce a high PSR low voltage LDO regulator based on a feed-forward ripple cancellation (FFRC) approach [10]. The proposed LDO topology preserves traditional loop dynamics structure, while providing high PSR over a wide fre- quency range. In addition, it enables the design for high supply currents and low quiescent current consumption. The paper is organized as follows: Section II discusses main PSR limitation sources in conventional LDOs. Section III presents the proposed FFRC-LDO. The stability analysis using a single bond-wire and 0018-9200/$26.00 © 2010 IEEE