LETTERS Label-free immunodetection with CMOS-compatible semiconducting nanowires Eric Stern 1 , James F. Klemic 2 , David A. Routenberg 2 , Pauline N. Wyrembak 5 , Daniel B. Turner-Evans 2 , Andrew D. Hamilton 5 , David A. LaVan 3 , Tarek M. Fahmy 1 & Mark A. Reed 2,4 Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms 1–10 . Suc- cessful solution-phase nanowire sensing has been demonstrated for ions 3 , small molecules 4 , proteins 5,6 , DNA 7 and viruses 8 ; how- ever, ‘bottom-up’ nanowires (or similarly configured carbon nanotubes 11 ) used for these demonstrations require hybrid fab- rication schemes 12,13 , which result in severe integration issues that have hindered widespread application. Alternative ‘top-down’ fabrication methods of nanowire-like devices 9,10,14–17 produce dis- appointing performance because of process-induced material and device degradation. Here we report an approach that uses comple- mentary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications. We demonstrate here that the limitations of fabricated nanowire- type devices can be overcome and that nanometre-scale sensors with little mobility degradation from bulk can be achieved. We have used ultrathin silicon-on-insulator wafers 9,10,18,19 , which require only lat- eral (in-plane, two-dimensional) active layer definition to achieve the nanometre dimensions needed for a nanowire-type device. Previous attempts with this approach used reactive-ion etching (RIE) of the active silicon layer, which unacceptably degraded device perform- ance 9,10 . To achieve the nanometre-scale dimensions necessary for sensitivity, we developed a fabrication process using an anisotropic wet etch: specifically, tetramethylammonium hydroxide, TMAH, which etches Si (111) planes about 100 times more slowly than all other planes 20 . This approach allows retention of pattern definition (of a masking oxide layer), and smoothes edge imperfections not aligned to the (111) plane. Previous work on TMAH-defined elec- tronic devices has shown excellent retention of electrical properties 18 , although not in configurations suitable for sensing. We show that ‘nanowire’ devices capable of sensing can be defined by TMAH etch- ing. Our approach uses commercially available (100) silicon-on- insulator wafers that yield trapezoidal cross-section nanowires with dominant Si (111) exposed planes, the preferred surface for selective surface functionalization 21 . First, we show that this process can be used reproducibly to gen- erate non-degraded devices that are narrower than their lithographic pattern definition 19 . A schematic depicting a completed device before removal of the masking oxide is shown in Fig. 1a. The anisotropic wet etch undercuts this masking oxide, whose lateral dimensions can be achieved with optical lithography, although it does not appreciably etch the degenerately doped (.10 20 cm 23 ) boron contacts 20 . A top- view scanning electron micrograph of a device with the oxide mask 1 Department of Biomedical Engineering, 2 Department of Electrical Engineering, 3 Department of Mechanical Engineering, 4 Department of Applied Physics, Yale University, P O Box 208284 New Haven, Connecticut 06511, USA. 5 Department of Chemistry, Yale University, P O Box 208107, New Haven, Connecticut 06511, USA. t S D G w a 200 nm b c e 0 300 Mobility (cm 2 V –1 s –1 ) 100 50 0 0 –10 –20 –30 –40 –5 –10 –15 10 μm I SD (10 –6 A) |I SD (A)| V SD (V) V GD (V) 30 100 300 Temperature (K) Hall Drift –1 –2 10 –7 10 –9 10 –11 10 –13 10 –15 –3 d f Figure 1 | Device fabrication and electrical performance. a, Schematic after anisotropic etch. The silicon-on-insulator active channel (yellow, width w and thickness t) is undercut etched, whereas degenerate leads (red) are etch- resistant. The source (S), drain (D), and underlying backgate (G) are labelled. b, c, Scanning electron micrograph (b) and optical micrograph (c) of a completed device. d, I SD (V SD )(w 5 50nm, t 5 25nm) for varying V GD (0 to 240 V, DV 521 V), illustrating p-type accumulation mode behaviour. e, | I SD | (V GD ) for V SD 521 V for forward (red) and reverse (black) sweep. f, Accumulation-mode Hall and drift mobilities versus temperature (w 5 300 nm, t 5 25 nm). Vol 445 | 1 February 2007 | doi:10.1038/nature05498 519 Nature ©2007 Publishing Group