306 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 3, MARCH 2002 Algorithms for Minimizing Standby Power in Deep Submicrometer, Dual- CMOS Circuits Qi Wang, Student Member, IEEE, and Sarma B. K. Vrudhula, Member, IEEE, Abstract—In this paper we address the problem of delay con- strained minimization of standby power of CMOS digital circuits that are implemented with dual- technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. Three efficient algorithms that operate on a gate level netlist are described. Each algorithm assigns one of two threshold voltages (high and low ) to each transistor so that the standby power dissipation is minimized without violating a user specified delay constraint. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any increase in delay when compared to the configuration in which all devices are at the low . Index Terms—CMOS, dual-threshold voltage, low-power CMOS, subthreshold current. I. INTRODUCTION M ICROELECTRONIC systems that are inactive or in a standby state waste energy because they are not per- forming useful computations. This is due to the current flow in MOSFETs that are in the off-state as well as the leakage of charge stored in their drain junctions. This energy consump- tion is a significant problem for battery operated devices such as pagers and cell phones. Traditionally, the power consumption in the standby mode ( ) has been negligible when compared to the dynamic power consumption ( ), which is the sum of the switching power consumption ( ) and the short circuit power consumption ( ). is the dominant component of . As transistor dimensions are scaled down, the supply voltage ( ) must also be reduced in order to reduce hot carrier effects [1]–[3], which result in performance degradation over time. Since the switching power dissipation is proportional to , reducing the supply voltage also has a first-order effect on reducing the switching power dissipation. The price paid for reducing the supply voltage is an increase in the gate delay due to the reduced drain current. This can be compensated for by reducing the device threshold voltage. The extent to which the threshold Manuscript received February 25, 1999; revised June 30, 2001. This paper was recommended by Associate Editor M. Pedram. This work was carried out at the NSF S/IUCRC Center for Low Power Electronics (CLPE) in the Electronics and Computer Engineering Department at the University of Arizona. CLPE was supported by the NSF under Grant EEC-9523338, the State of Arizona, and a consortium of companies from the microelectronics industry. Q. Wang is with the Cadence Design Systems, San Jose, CA 95134 USA (e-mail: qwang@cadence.com). S. B. K. Vrudhula is with the Electrical and Computer Engineering Depart- ment, University of Arizona, Tucson, AZ 85721 USA (e-mail: sarma@ece.ari- zona.edu). Publisher Item Identifier S 0278-0070(02)01784-0. voltage can be reduced is determined by the noise margins and the increase in the subthreshold current [4], [5]. An approximate expression for the subthreshold current is given by [6] subthreshold (1) where , , and are the gate, source, and drain terminals, is the threshold voltage, is the thermal voltage and and are technology-dependent constants. Equation (1) indicates that for , subthreshold is practically independent of . Thus, with (standby), the consequence of lowering to compensate for the increased delay that results when is reduced is an exponential increase in the subthreshold current. Simulation results presented in [6] show that for low threshold voltages, the power dissipation ( ) in this standby mode is of the same order as the switching power dissipation ( ). In small geometry MOSFETs, the drain-induced barrier lowering (DIBL) effect results in effectively reducing the channel length, resulting in a lower and increasing the subthreshold leakage. One way to reduce the standby power dissipation is to apply a reverse substrate bias to the chip. In [7] it is shown that there is an optimum reverse substrate bias for each technology gen- eration that minimizes the standby power consumption for that technology. An alternative is to use a dual- process which al- lows both low and high transistors on the same chip. A circuit design style, called multithreshold CMOS (MTCMOS) [8], [9], exploits this capability to achieve high performance and low power with low voltage operation. A 1-V DSP chip using MTCMOS has been fabricated and tested [10]. Devices with two different threshold voltages using the same strip of diffu- sion are also possible. This is done by increasing the spacing between the diffusion strips and using an additional mask to modify the [11], [12]. The processor design described in [12] uses devices with two distinct threshold voltages, where low transistors are manually inserted into custom macros to improve delay. The emergence of dual- processes provides a new opportu- nity for circuit designers to make tradeoffs between power and delay. The two ends of the spectrum correspond to the situa- tions where all devices are at the low threshold voltage ( ) and all devices are at the high threshold voltage ( ). In this paper we present algorithms that partition the devices in the cir- cuit into two subsets, and , corresponding to devices at and , respectively. The algorithms that determine these subsets can start from either of the two extremes. The first algo- rithm (Algorithm I) starts with all devices at and identifies the subset whose threshold voltage can be set to such 0278-0070/02$17.00 © 2002 IEEE