Solid-State Electronics Vol. 35, No. 7, pp. 985-991, 1992 0038-1101/92 $5.00 + 0.00 Printed in Great Britain. All rights reserved Copyright © 1992 Pergamon Press Ltd CAPACITANCE METHOD FOR DETERMINATION OF LDD MOSFET GEOMETRICAL PARAMETERS P. VITANOV, T. DIMITROVA, R. KAMBUROVA and K. FILLJOV Institute of Microelectronics, 1784 Sofia, Bulgaria (Received 5 March 1991, in revised form 25 August 199I) AImtraet--A simple capacitance method for determination of feature sizes in LDD devices is presented. It is based on direct measurement of the intrinsic MOS capacitances using a suitable multitransistor test structure. Experimental results for conventional and inverse T, lightly-doped drain MOSTs with 1.5/tm drawn channel length are shown. I. INTRODUCTION The LDD device can be described completely by the following important parameters: n junction- to-junction spacing, n + junction-to-junction spac- ing, length of n region, length of spacer and gate~lrain-source overlap. The influence of these parameters on LDD device characteristics and re- liability is essential. Various methods have been proposed to determine the physical channel length of MOS transistors with abrupt source~lrain junctions. The known channel length measuring techniques of MOS devices can be divided into two categories. The first is a channel conduction technique[l-3] and the second is a capaci- tance measurement[4-6]. However, if the source~irain junctions are not abrupt (for example in LDD devices) the applica- bility of the conventional conduction technique is questionable. Due to the fact that part of the n- region under or near the gate is modulated by the gate bias, the source~drain series resistance of an LDD device becomes gate-voltage depen- dent[7]. The series resistance variation for LDD or DDD devices makes all channel cotlduction techniques even less accurate for more advanced technologies. The capacitance technique, on the other hand, is more accurate but difficult to im- plement due to the very low capacitance of MOS devices. In order to avoid the resolution constraint of the measurement, an alternative for measuring the capacitances of small devices is to use a large number of devices connected in parallel[5]. For example, a test structure consisting of 1500 MOSTs connected in parallel with a designed channel length of 1.5 gm and a channel width of 25/tm has the same net gate capacitance as a gate area of 56,250 pm 2. This paper describes a simple capacitance measure- ment method by which geometrical device par- ameters of LDD MOSFETs can be determined. The results obtained are compared with results of other methods. 2. EXPERIMENTALTECHNIQUE A detailed description of the capacitance technique used is given in Ref.[5]. The capacitance measure- ments are done on a multitransistor structure consist- ing of n number of MOSTs connected in parallel with a resultant width n W. When the polysilicon line of the multitransistor structure is quite long (nW>>Ldra~n) and is contacted only at one place, a distributed delay line with parameters R = rsLd .... and C = CoxLd .... (where r s = sheet resistance of the polysilicon line, Cox = capacitance of the gate oxide per unit area, Ld .... = the drawn channel length of a transistor in the multitransistor strucutre) will appear. If the ca- pacitance measurements are done at fro = 1 MHz, the time distribution of the test signal along the polysili- con line can be higher than the period T= 1/fm. Effectively this will result in a decrease of the measured capacitance compared to the real value[7]. The problem can be avoided using lower frequencies or using an appropriate topology of the test structure. A suitable solution is to use a multitransistor struc- ture in which small groups of 3-4 gates are connected by metal lines (see Fig. 1). Then the partial length of the polysilicon line (signified with P) along which the test signal is spread, is short enough. The parasitic capacitances owing to field oxide region and Al-polysilicon overlap length are designed to be minimum. The net sum of these parasitic capacitances has to be two orders of magnitude smaller than the total gate capacitance. In order to reduce the errors due to LOCOS bird's beak, the channel width W has to be long enough compared to the channel length Zdrawn . Two capacitance measurements in strong accumu- lation are needed for the determination of effective channel length Lee (the distance between the two 985