ARTICLES Structural properties of 〈111〉B-oriented III–V nanowires JONAS JOHANSSON 1 *, LISA S. KARLSSON 2 , C. PATRIK T. SVENSSON 3 , THOMAS M ˚ ARTENSSON 1 , BRENT A. WACASER 1 , KNUT DEPPERT 1 , LARS SAMUELSON 1 AND WERNER SEIFERT 1 1 Solid State Physics, Lund University, PO Box 118, SE-221 00 Lund, Sweden 2 National Centre for High Resolution Electron Microscopy (nCHREM)/Polymer & Materials Chemistry, Lund University, PO Box 124, SE-221 00 Lund, Sweden 3 QuNano AB, Stora Fiskaregatan 13E, SE-222 24, Lund, Sweden *e-mail: jonas.johansson@ftf.lth.se Published online: 18 June 2006; doi:10.1038/nmat1677 Controlled growth of nanowires is an important, emerging research field with many applications in, for example, electronics, photonics, and life sciences. Nanowires of zinc blende crystal structure, grown in the 〈111〉B direction, which is the favoured direction of growth, usually have a large number of twin-plane defects. Such defects limit the performance of optoelectronic nanowire-based devices. To investigate this defect formation, we examine GaP nanowires grown by metal-organic vapour-phase epitaxy. We show that the nanowire segments between the twin planes are of octahedral shape and are terminated by {111} facets, resulting in a microfaceting of the nanowires. We discuss these findings in a nucleation context, where we present an idea on how the twin planes form. This investigation contributes to the understanding of defect formation in nanowires. One future prospect of such knowledge is to determine strategies on how to control the crystallinity of nanowires. S emiconductor nanowires are promising in many applications in photonics, life sciences, electronics, and physics 1 . One of the areas where nanowires are of major interest is the miniaturization of electronics. Conventional complementary metal oxide semiconductor (CMOS) technology is predicted to soon face a limit where further downscaling is not feasible. What limits the size of a MOS transistor is the increasing leakage current with decreasing size. On the other hand, the packing density of such devices is limited by the increasing power dissipation with increasing density. Some of these obstacles could be overcome with nanowires. Field-effect transistors 2 , single- electron transistors 3 , and memory devices 4 , all with feature sizes smaller than practically possible in CMOS, have been demonstrated in nanowires. Nanowires may also serve as diodes, resistors, or interconnects, making ultra-compact device integration possible. In fact, III–V heterostructure nanowires can be grown epitaxially on Si (ref. 5). This enables integration of optoelectronic III–V devices with Si technology, which is a long-time goal for the semiconductor industry. Hybrid circuits, combining nanowire devices with conventional CMOS, but without epitaxial contact between the wires and the Si, have also been fabricated and demonstrated as prototypes 6 . One effect that can limit the performance of optoelectronic nanowire devices is the large number of crystal imperfections in the 〈111〉B-oriented III–V wires. This is particularly unfortunate because this is the most favourable direction for wire growth. The imperfections are twin planes normal to the growth direction and they have been reported in nanowires made of various materials, for example, GaP (refs 7,8), InP (ref. 9), ZnSe (ref. 10), Zn 2 SnO 4 (ref. 11), independent of the fabrication method. Twin planes have also been observed in Si nanowires made by laser ablation 12,13 , but have not, to our knowledge, been reported in Si nanowires controllably grown in the 〈111〉 direction, following the epitaxial orientation of the substrate 14,15 . Twin planes are also abundant in bulk III–V semiconductors 16 . The purpose of this investigation is to present and explain the three-dimensional (3D) geometry of 〈111〉B-oriented nanowires with zinc blende crystal structure and to give an explanation 574 nature materials VOL 5 JULY 2006 www.nature.com/naturematerials Nature Publishing Group ©2006