Tunneling field-effect transistor with a strained Si channel and a Si 0.5 Ge 0.5 source Q.T. Zhao a,⇑ , W.J. Yu a,b , B. Zhang a,b , M. Schmidt a , S. Richter a , D. Buca a , J.-M. Hartmann c , R. Luptak a , A. Fox a , K.K. Bourdelle d , S. Mantl a a Peter Grünberg Institute 9 (PGI 9), JARA-FIT, Forschungszentrum Juelich, 52425 Juelich, Germany b Shanghai Institute of Microsystem and Information Technology, CAS, 200050 Shanghai, China c CEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble, France d SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France article info Article history: Available online 19 May 2012 Keywords: Tunnel FET Strained Si Subthreshold swing SiGe abstract We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel and a compressively strained Si 0.5 Ge 0.5 source. The device shows good performance with an average subthresh- old swing S of 80 mV/dec over a drain current range of more than 3 orders of magnitude. We observed that the on-current increases exponentially with the back gate voltage. At a back gate voltage of 8 V, the on-current was enhanced by a factor of 1.6. The back gate also improves the on/off current ratio. Low temperature measurements show a slightly temperature dependent S, characteristic for a tunneling dominated device. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction Steep slope devices with inverse subthreshold slopes (SS) <60 mV/dec are required in order to reduce both, the active and the static power consumptions. One promising device is the band-to-band tunneling (BTBT) field-effect transistor (TFET) due to the potential for extremely low off-current (I off ), and for the pos- sibility to lower the subthreshold swing S, beyond the 60 mV/dec limit of a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) (at 300 K) [1–8]. However, almost all Si based TFETs exhibit a low on-current I on due to the rather small tunneling probability in doped Si junctions. The experimentally obtained subthreshold swing which is drain current dependent is much larger than 60 mV/dec at 300 K as the drain currents I d > 10 10 A/lm [4]. Using the Wentzel–Kramers–Brillouin (WKB) approximation the tunneling probability T WKB is given by [2]: I / T WKB  exp  4k ffiffiffiffiffiffiffiffiffi 2m  p E 3=2 G 3q hðDU þ E G Þ  ! ð1Þ Here k is the screening length, depending on the doping profile and the device geometry, m  the effective carrier mass, E G the bandgap, q the elementary charge and  h the reduced Planck’s constant. DU denotes the energy difference between the valence band in the source and conduction band in the channel. In order to increase the tunneling currents smaller band gap materials with small effec- tive mass are required. SiGe and Ge provide higher tunneling prob- abilities due to their small bandgaps [5–12]. Also tensile strained Si (sSi) which has a smaller bandgap than Si helps to improve the tun- neling currents [13,14]. However, homogeneous structure device using the same bandgap material for source/drain and channel suf- fers ambipolar behavior which limits the I on /I off ratio and SS [9,10]. Heterostructure n-TFETs using poly-Ge as source showed high I on / I off ratios with suppressed ambipolar behavior [6]. Furthermore, simulations of TFETs with SiGe source and sSi channel showed very promising device performance [8]. In this paper we present experimental results for an n-TFET with improved I on by exploiting the properties of a highly strained Si/SiGe heterostructure. As compared to Si these devices benefit from the smaller band gap energies of both, sSi and SiGe, and the valence band offset between these two layers. 2. Device fabrication N-channel TFETs were fabricated on sSi/Si 0.5 Ge 0.5 heterostruc- ture grown on 12 nm strained SOI (SSOI) substrates. The SSOI layer is biaxially tensile strained (0.8%) with slightly p-doped (1  10 15 cm 3 ). Si 0.5 Ge 0.5 layer with a thickness of 25 nm and 5 nm thick Si cap layer were grown using reduced pressure chem- ical vapor deposition [15]. In this case, the Si 0.5 Ge 0.5 layer is under lower biaxial compressive strain compared to the layer grown on unstrained SOI. The Si cap layer is also tensile strained. The TFET fabrication process is described in Fig. 1. First, the Si 0.5 Ge 0.5 layer was implanted with BF 2 + at an energy of 3 keV to a dose of 2  10 15 cm 2 , then the source area was defined by selectively 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.04.018 ⇑ Corresponding author. E-mail address: q.zhao@fz-juelich.de (Q.T. Zhao). Solid-State Electronics 74 (2012) 97–101 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse