IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 3, MARCH 2005 397 Asymmetric Halo CMOSFET to Reduce Static Power Dissipation With Improved Performance Aditya Bansal, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract—In this paper, we show the benefits of using asym- metric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% re- duction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates. Index Terms—Band-to-band tunneling, halo implants, MOSFET, NAND gate, NOR gate, process variations. I. INTRODUCTION S CALING of MOS transistors has been extensively studied to improve circuit performance and packing density in the future very large-scale integrated (VLSI) circuits. However, the device scaling of MOSFETs is slowly approaching the phys- ical limits of fabrication processes and devices. With each future technology generation, the dimensions of a MOSFET are dras- tically scaled down. Gate oxide cannot be scaled beyond a limit as gate direct tunneling leakage current increases exponentially with oxide thickness scaling. Also, voltage scaling is limited by the desired power supply-to-threshold voltage ratio. Threshold voltage cannot be scaled too much to maintain adequate off-currents. Thus, with nonscaled gate oxide thick- ness and supply voltage, short-channel effect (SCE) degrades in these devices. To suppress the SCE, a laterally nonuniform (halo implants) doping profile has been suggested in [1]. Also, later- ally asymmetric channel profile, i.e., different source and drain- side peak halo doping concentrations (PHDC), was studied to improve hot carrier reliability [2] as well as performance [3]. In super-halo nMOSFETs, at high drain-to-substrate volt- ages, the n drain extension doping is reverse biased to the p-type halo implant. Since, supply voltage is not scaled as expected, there is high electric field at the n p junction. This results in significant current flow due to the tunneling of electrons from the valence band of the p-region into the Manuscript received October 7, 2004. This work was supported in part by Semiconductor Research Corporation. The review of this paper was arranged by Editor T. Skotnicki. The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: bansal@ ecn.purdue.edu; kaushik@ecn.purdue.edu). Digital Object Identifier 10.1109/TED.2005.843969 conduction band of the n-region. This reverse biased diode junction band-to-band tunneling (RBDJ BTBT) current density can be given by Kane’s model [4], [5] where is the energy bandgap, is the applied reverse voltage across the junction, is the electric field and is the effec- tive mass of the electrons. RBDJ BTBT current is significant in the sub-50-nm regime, where high doping concentration of halo implants is necessary to suppress SCE. It is shown that SCE are mainly controlled by the sourceside halo doping [6]. In the most popular CMOS implementation of the circuits, the drain–sub- strate junction is reverse biased and leaks RBDJ BTBT current. Therefore, drainside PHDC can be decreased to reduce RBDJ BTBT current. However, no extensive study has been done to explore the advantages of asymmetric halo devices (different source and drainside halos) in leakage reduction at iso-perfor- mance for the MOSFETs down to 25-nm channel lengths. In this paper, static leakage and performance in asymmetric halo (AH) transistors have been compared, at device and cir- cuit level, with conventional symmetric halo (SH) transistors. Doping contours are shown in Fig. 1. SH transistors have both source and drainside PHDCs of same concentration. AH transistors have different drain and sourceside PHDCs. Source side PHDC is normally higher than drainside PHDC to control SCE [6]. Doping profiles of SH and AH MOS- FETs are optimized to achieve minimum total leakage at iso on-current. Two-dimensional device and mixed-mode circuit simulations have been performed in a Taurus Device Simulator [7]. Taurus solves one-dimensional Schroedinger equations self-consistently with Poisson equations. It uses Kane’s model to compute the band-to-band tunneling carrier density. The carriers generated because of the band-to-band tunneling are included self-consistently. II. DEVICE DESIGN The basic device, on which modifications to doping pro- file are made, is a 25-nm channel length, well-tempered bulk-MOSFET from the Massachusetts Institute of Technology [8]. Table I shows the device geometry and physical parameters. Doping profiles have been optimized by varying the concentra- tion and position of PHDC. Moving the peak halo up on the sourceside minimizes the penetration of lateral electric field from the drain to the source increasing the threshold voltage [9]. Also, moving down the position of peak halo degrades SCE and may result in punchthrough. Therefore, the position 0018-9383/$20.00 © 2005 IEEE