Introductory Invited Paper Electron transport through broken down ultra-thin SiO 2 layers in MOS devices Enrique Miranda a,b, * , Jordi Su~ n e c a Departamento de F  ısica, Facultad de Ingenier  ıa, Universidad de Buenos Aires, Paseo Colon 850, Buenos Aires 1063, Argentina b Consejo Nacional de Investigaciones Cient  ıficas y T ecnicas (CONICET), Argentina c Departament d’Enginyeria Electr onica, Universitat Aut onoma de Barcelona, 08193 Bellaterra, Spain Received 25 August 2003 Abstract When the gate insulator of a metal–oxide–semiconductor structure is subjected to electrical stress, traps or defects are progressively generated inside the oxide that eventually lead to the formation of a low-resistance conducting path between the electrodes. The occurrence of such event can be detected either as a gradual or as a sudden change in the system’s conductance and is associated with the appearance of a localized conduction mechanism in parallel with the area-distributed tunneling current. According to the magnitude and shape of the resulting current–voltage character- istic, the failure mode is usually referred to as soft or hard breakdown. However, because of the random nature of the phenomenon, interpretation and modelling of the electron transport mechanism involved has turned out to be very challenging from the physical point of view. Several models have been proposed to this aim, which can be classified basically according to the underlying mechanism: junction-like, hopping, percolation and tunneling conduction. Within this latter mechanism we can mention direct, Fowler–Nordheim, trap-assisted, resonant, inelastic tunneling and point contact conduction. In this paper, after an overview of a variety of physical and engineering aspects of post-breakdown, we critically examined the foundations and limitations of the proposed conduction models in the light of others and ours experimental results, putting special emphasis on those approaches providing final closed expressions. Ó 2003 Elsevier Ltd. All rights reserved. 1. Introduction Although the problem of electron transport through broken down dielectric layers in metal–oxide–semicon- ductor (MOS) devices has been studied for more than about four decades [1], nowadays, there is a renewed interest in this topic mainly because of its reliability implications for the field of microelectronics devices and circuits [2]. In particular, breakdown of the gate insu- lator in a MOSFET device may imply a partial or total loss of the transistor effect as well as an increase in standby power consumption, which may have unpre- dictable consequences for the overall functionality of a circuit application. Because of these reliability concerns, understandably, most of the effort during the past 30 years was focused on investigating the driven forces behind the SiO 2 dielectric breakdown [3–5]. A variety of models connecting the degradation process with the stress conditions, written in terms either of the oxide field or applied voltage, have been proposed to this aim, but, despite the huge amount of data and publica- tions, no consensus has been reached for the root causes of dielectric breakdown yet and the contro- versy still persists [6–9]. However, particularly in recent years, researchers have begun to investigate in depth what happens beyond the occurrence of such event not only for practical purposes but also for the academic interest itself. As we will see, even though much more * Corresponding author. Current address: Departamento de F  ısica, Facultad de Ingenier  ıa, Universidad de Buenos Aires, Paseo Colon 850, Buenos Aires 1063, Argentina. E-mail addresses: emirand@fi.uba.ar (E. Miranda), jordi. sune@uab.es (J. Su~ n e). 0026-2714/$ - see front matter Ó 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2003.08.005 Microelectronics Reliability 44 (2004) 1–23 www.elsevier.com/locate/microrel