Microprocessing and Microprogramming Journal, vol. 39, pp. 251-254, December 1993 1 VLSI Implementation of Digit-Serial Arithmetic Modules L. Bisdounis, D.E. Metafas, A.M. Maras * , C. Mavridis VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece. * Department of Electronic & Computer Engineering, Technical University of Crete, 73100 Chania, Greece. ABSTRACT This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach. 1. INTRODUCTION The digit-serial techniques are ideal in digital signal processing as they offer the flexibility which is needed in order to exploit the potential of the available technology. Bit-serial implementations process one bit at a time and are suitable for low speed applications such as communications and speech processing [1]. On the other hand very high sample rates in radar, video and image processing call for fully bit-parallel implementations which process all input bits of a word or sample in one clock cycle [2]. In digit-serial computations, data words are divided into digits and transmitted serially one digit at a time between operators. Architectural synthesis based on digit-serial modules offers the structured design approach needed in order to find the best solution for the application that concerns the tradeoffs between cost, speed, efficient area utilisation, throughput, clock distribution, I/O pin limitation and power dissipation. Hartley et al. [3] explored some digit- serial structures, while Parhi [4] proposed an approach to the design of digit-serial arithmetic modules that transforms a bit-serial structure into a digit-serial structure using an unfolding transformation algorithm. Although the approach presented in [4], eased the complexity of the