IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009 3181 A 1-GSample/s, 15-GHz Input Bandwidth Master–Slave Track-and-Hold Amplifier in InP DHBT Technology Yves Bouvier, Achour Ouslimani, Agnieszka Konczykowska, Senior Member, IEEE, and Jean Godin Abstract—A fully differential master–slave track-and-hold amplifier is designed and fabricated in a 210-GHz- InP DHBT process. Input bandwidth of 15 GHz, total harmonic distortion lower than -39 dB and a third harmonic rejection greater than 45 dB are measured for 1 GSample/s and 4 dBm single-ended input signal. Time domain measurements demonstrate the performances of dual track-and-hold amplifier for Nyquist, over-sampling and sub-sampling conditions. Design tradeoff for master and slave blocks are presented. Experimental results obtained for different feed-through capacitors show the effects of on band- width and isolation. Index Terms—Analog-to-digital converter (ADC), InP, DHBT, master–slave, sub-sampling, track-and-hold amplifier (THA). I. INTRODUCTION T RACK-AND-HOLD amplifiers (THAs) are an important block of analog-to-digital converters (ADCs) which are widely used in digital-signal processing systems. These cir- cuits attract a lot of attention for many industrial applications. In optical communication, ADC can improve decision circuit performances working in over-sampling conditions. In wireless communication, they allow to reduce the down-conversion circuit complexity operating in sub-sampling conditions. Simple THA circuits have been reported for over-sampling applications [1]–[5]. A 10-bit, 1-GSample/s dual-THA fabricated in SiGe BiCMOS technology is presented [6] in Nyquist condition. We have presented a 20-GSample/s THA with 20 GHz nonlinear bandwidth for over-sampling applications [5] and 1-GSample/s dual-master–slave dual track-and-hold amplifier (DTHA) for sub-sampling applications [7]. In this paper, we present a fully differential DTHA and its master THA for 1-GS/s sub-sam- pling applications designed and fabricated in a 210-GHz- InP DHBT process. Large-signal measured input bandwidth of 15 GHz and a track-mode bandwidth over 20 GHz are obtained for DTHA and THA circuits, respectively. For 1 GSample/s and 4 dBm single-ended input signal, the DTHA demonstrate a total harmonic distortion lower than -38.7 dB and a third harmonic rejection greater than 45.1 dB. Master track mode measurements Manuscript received May 12, 2009; revised July 09, 2009. First published November 03, 2009; current version published December 09, 2009. This work was supported in part by the French DGA (Direction G n rale de l’Armement). Y. Bouvier, A. Konczykowska, and J. Godin are with Alcatel-Thales III-V Laboratory, Marcoussis 91460, France (e-mail: jean.godin@3-5lab.fr). A. Ouslimani is with ECS-ENSEA, Cergy-Pontoise 95014, France. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2009.2033252 Fig. 1. Large-band DTHA block architecture. show a bandwidth over 20 GHz, Total harmonic distortion lower than -23 dB and a third harmonic rejection greater than 35 dB for 4 dBm single-ended input signal. Section II deals with the circuit design. Section III presents the fabricated circuit and the experimental setup. Section IV discuss the experimental results. II. CIRCUIT DESIGN Fig. 1 shows DTHA block architecture which is composed of two stages: master stage and slave stage. -phase shift clock signal is set between the master and the slave stage for the sub- sampling operation. Each stage, composed of a core, an input data buffer, and a clock buffer, is designed, fabricated and char- acterized in order to optimize the performances of each block apart. The master stage is the main block which determines the linearity and the bandwidth of the DTHA. On the other hand, the slave stage rules the isolation. The two stages have the same topology. In particular, the master stage is optimized to obtained 0018-9480/$26.00 © 2009 IEEE Authorized licensed use limited to: Alcatel Lucent. Downloaded on December 29, 2009 at 04:34 from IEEE Xplore. Restrictions apply.