Low Power Single Core CPU for a Dual Core Microcontroller Rajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Vivek Periye Amrita Vishwa Vidyapeetham, Amritapuri, Kollam - 690525, Kerala, India rajeshm@am.amrita.edu,ashwinmohan@ieee.org,shekhil@ieee.org,tanmaymrao@ieee.org,vivek_p@ieee.org Abstract—Microcontrollers that can provide higher performance while maintaining low power consumption is a key research area. Power aware high performance microcontrollers are critical in embedded system applications. Our paper mainly focuses on the low power implementation of a Dual Core Microcontroller. A Dual Core Microcontroller consumes less power and area than two coupled Single Core Microcontrollers. We have implemented a Low Power Single Core CPU for a Dual Core Microcontroller in Verilog HDL and synthesized the design using Synopsys Design Compiler and Xilinx 10.1. We have also given the experimental results for the low power techniques implemented. Keywords-Microcontroller; Core; Low Power; CPU; Datapath; Performance; Dual Core I. INTRODUCTION Microcontrollers have lot of applications in automotive, safety, and other embedded applications. Earlier the major design constraints were performance, frequency of operation and area. Power consumption was just an afterthought. Due to the advent of battery-run embedded and portable devices in large scale, power consumption has also become one of the foremost microcontroller design parameters. By saving power, we can increase the battery life, improve the reliability of the system, reduce the cooling components, lower system cost and reduce environmental issues [7], [10]. Power consumption reduction without sacrificing the performance has become an important design criteria. The performance of a Single Core can be improved by increasing the operating frequency. But simply increasing the operating frequency won’t improve the overall system performance since memory elements should also keep in pace with the operating frequency. The power consumption also increases when the clock frequency is increased. Thus we should aim at boosting the performance without increasing the clock frequency. In a typical microcontroller, all the peripherals present won’t be needed for a particular application. As a result of leakage current, the pins also consume a portion of the total power. A Dual-Core Microcontroller can solve these problems. Instead of using a single High-Speed Core, we can use two cores. Both the cores can share the peripherals, buses, memories and the input-output pins, thus chip area can be saved. When two cores are on the same die, the inter- core communication becomes faster as the signals has to travel a shorter time period and there will be less degradation of signals. Thus communication between the two different microcontrollers won’t affect the performance of the microcontrollers. Hence a Dual Core Microcontroller uses less power than two coupled Single Core Microcontrollers [1], [2], [3]. Companies like Renesas, ST Microelectronics, Atmel and Maxim have come up with Dual Core Microcontrollers. Dual Core Microcontrollers find lot of applications in automotive industry, Car Navigation System, Industrial controls and Cryptographic Systems. II. INSTRUCTION SET ARCHITECTURE (ISA) The microcontroller can support up to 21 instructions. The instruction has fixed operand fields. The pipelined datapath can deliver one instruction per clock cycle (Single issue). Each instruction is 29 bits wide. The instruction set can be classified as Byte type Instructions, Bit type Instructions and Control Instructions. The Byte type instructions can be further classified as Register-Register Instructions and Register-Immediate Instructions. A basic instruction format is shown in Fig. 1. The ISA was designed with a low power perspective. Opcode’s 5 th bit and 4 th bit represent the type of instruction [5]. III. IMPLEMENTATION OF SINGLE CORE We have implemented an 8-bit core which has a Harvard Architecture- separate Program and Data Memories. The core supports the mentioned Instruction Set. The microcontroller core is implemented as a pipelined architecture to improve the performance. The core consists of three stages- Fetch, Decode and Execute/Write Back. In the first clock cycle instruction will be fetched from the Program Memory, in the second clock cycle operands will be fetched from the memory and control signals will be generated. In the third clock cycle instructions will be executed and the result will be written back to the Data Memory. The data and control signals needed in the later stages will be propagated through the pipeline registers. The datapath of Single Core CPU is shown in Fig. 2. 28 24 23 16 15 8 7 0 Figure 1. Basic Instruction format Opcode Destination reg Source reg 1 Source reg 2 Third International Conference on Emerging Trends in Engineering and Technology 978-0-7695-4246-1/10 $26.00 © 2010 IEEE DOI 10.1109/ICETET.2010.76 791 Third International Conference on Emerging Trends in Engineering and Technology 978-0-7695-4246-1/10 $26.00 © 2010 IEEE DOI 10.1109/ICETET.2010.76 791 Third International Conference on Emerging Trends in Engineering and Technology 978-0-7695-4246-1/10 $26.00 © 2010 IEEE DOI 10.1109/ICETET.2010.76 791 Third International Conference on Emerging Trends in Engineering and Technology 978-0-7695-4246-1/10 $26.00 © 2010 IEEE DOI 10.1109/ICETET.2010.76 791