Hybrid Integration of Silicon Nanophotonics with 40nm-CMOS VLSI Drivers and Receivers Hiren D. Thacker, Ivan Shubin, Ying Luo, Joannes Costa, Jon Lexau * , Xuezhe Zheng, Guoliang Li, Jin Yao, Jieda Li, Dinesh Patil , Frankie Liu * , Ron Ho * , Dazeng Feng ° , Mehdi Asghari ° , Thierry Pinguet + , Kannan Raj, James G. Mitchell * , Ashok V. Krishnamoorthy and John E. Cunningham Oracle Labs, San Diego, CA * Oracle Labs, Menlo Park, CA Rambus, previously with Oracle Labs, Menlo Park, CA ° Kotura Inc., Monterey Park, CA + Luxtera Inc., Carlsbad, CA Oracle Labs, 9515 Towne Centre Drive, San Diego, CA 92121 Phone: (858) 526-9442, Fax: (858) 526-9176, E-Mail: hiren.thacker@oracle.com Abstract Oracle’s scalable hybrid integration technology platform enables continuing improvements in performance and energy efficiency of photonic bridge chips by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultralow power high-performance photonic interconnects for future computing systems. Herein, we report on our second generation of photonic bridge chips comprising electronic drivers and receivers built in 40 nm bulk CMOS technology attached to nanophotonic devices, fabricated using SOI-photonic and 130 nm SOI-CMOS photonic technologies. Hybrid integration by flip-chip bonding is enabled by microsolder bump interconnects scaled down from our previous generation effort and fabricated on singulated dies by a novel batch processing technique based on component embedding. Generation-on-generation, the hybrid integrated Tx and Rx bridge chips achieved 2.3x and 1.7x improvement in energy efficiency, respectively, while operating at 2x the datarate (10 Gbps). I. Introduction Within the past decade, the semiconductor computing industry has developed multicore and multithreaded core processors to overcome the challenges and shrinking benefits of traditional technology scaling. Multichip systems built using these components will require massive amount of off- chip bandwidth and low latency chip-to-chip links at the lowest energy cost possible. Wavelength-division multiplexed (WDM) silicon photonics has the potential to provide a solution for this immense interconnect problem [1]. Within the Ultraperformance Nanophotonic Intrachip Communication (UNIC) program at Oracle, we are aggressively building a portfolio of technologies in active and passive nanophotonic devices (modulators, detectors, WDM components), circuits, and multichip packaging to achieve the vision of 15 Gbps, 300 fJ/bit photonic links between computing elements in a large array “Macrochip” [1]1. Juxtaposition of nanophotonic devices and VLSI circuits on a common silicon substrate interconnected by low parasitic on-chip interconnects is perhaps the most intimate method for integrating electronics and photonics. Realistically, however, the design and process integration of nanophotonic devices on CMOS platforms presently lags a few technology generations behind the state-of-the-art technology. Trading-off component performance for monolithic co-integration by using lesser than the best available CMOS technology would not lead to the lowest energy per bit links. Instead, hybrid integration of best-in-breed photonic and electronic components, built on individually optimized technology platforms, is a much more pragmatic approach to achieving peak performance. In such a hybrid integrated component, the chip-to-chip interconnects must have ultralow parasitics. Previously [2], we reported on the hybrid integration by flip-chip bonding of 130 nm SOI-CMOS photonic and SOI- photonic chips to 90 nm bulk CMOS ICs. The transmitter (Tx) and receiver (Rx) bridge chips resulting from that effort achieved ultralow-power performance of 1.6 mW [2] and 3.4 mW [4], respectively, at 5 Gbps thereby validating this approach for creating low-power integrated components. The integration was enabled by microsolder bump interconnects fabricated on one or both chips, which had an average resistance of 0.6 Ω/bump and an estimated capacitance of 20- 25 fF/bump [2]. Figure 1. Schematic of a hybrid bond. Figure 1 shows a schematic of a hybrid bond. It comprises under-bump-metallization (UBM) and a microsolder bump. The UBM provides a stable, low resistance contact to the chip’s I/O pads, provides a strong adhesion interface between the die bondpad and bump materials, and prevents diffusion of the bump materials into the chip. The microsolder bumps sit atop the UBM and get fused into opposing pads during flip-chip bonding, thereby creating a high conductivity chip- 978-1-61284-498-5/11/$26.00 ©2011 IEEE 829 2011 Electronic Components and Technology Conference