1498 IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 11, NOVEMBER 2011 Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction Chun-Hsing Shih and Nguyen Dang Chien Abstract—This study presents a new sub-10-nm tunnel field- effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The ON-state tunneling barrier around the source was narrowed and lowered to demonstrate a high ON-current; simultaneously, the OFF-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage cur- rent. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes. Index Terms—Bandgap engineering, graded Si/Ge heterojunc- tion, short-channel effect, tunnel field-effect transistor (TFET). I. I NTRODUCTION T UNNEL field-effect transistor (TFET) has demonstrated the potential to surpass the subthreshold swing limit of 60 mV/dec at 300 K, both theoretically and experimentally [1]–[3], and serves as an attractive candidate for low-power applications [1], [4]. A minimized subthreshold swing with a high ON-current and low OFF-current is the key requirement for a TFET to be an ideal switching device. A silicon-based TFET exhibits a low OFF-current and minimized subthreshold swing; however, it suffers from a low ON-current because of its relatively high energy bandgap [1], [3], [5]. Small-bandgap semiconductors, such as SiGe and Ge, have been introduced in TFET devices for boosting the ON-current. Unfortunately, ambipolar OFF-current is increased correspondingly [5], [6]. Several gate engineering methods using high-k gate dielectrics have been utilized to enhance the ON-current and suppress the OFF-current [7]–[9]. Alternatively, channel engi- neering techniques using asymmetric silicon–germanium sub- strates have been employed to generate favorable switching characteristics [4], [10]–[13]. Although those approaches have promoted the merits of long-channel TFET devices, scaling TFET length (L g ) into sub-20-nm regimes is still a consider- able challenge [14]. Introducing high-k dielectrics and double- gate structure offers a stronger gate control to salvage TFETs Manuscript received July 12, 2011; revised July 29, 2011; accepted August 2, 2011. Date of publication September 25, 2011; date of current version October 26, 2011. The review of this letter was arranged by Editor X. Zhou. The authors are with the Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan (e-mail: shihch@ncnu.edu.tw). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2011.2164512 partly from short-channel effect [14], [15]. However, short- channel effect is extremely pronounced into sub-20-nm regimes due to the presence of direct drain-to-source tunneling [9] and the penetration of lateral electrical field [14]. Using small- bandgap semiconductors widens active tunneling regions, con- straining the device scaling further. To scale TFETs into sub-10-nm regimes, this study proposes a new graded Si/Ge heterojunction to tailor the on–off switch- ing tunneling barrier. Using this architecture, both the height and width of the tunneling barrier are controlled precisely using gate voltages to ensure an ideal device switching. A 2-D simulation [16] was performed to study a p-body TFET us- ing a graded Si/Ge heterojunction. Section II describes the device structures and simulation parameters of TFET devices. Section III discusses the mechanism of bandgap engineering and presents the device characteristics of the ON-/OFF-current and subthreshold swing in sub-10-nm TFET devices. II. DEVICE STRUCTURES AND SIMULATION PARAMETERS Fig. 1(a) shows the schematic sketch of a p-body TFET with a graded Si/Ge heterojunction, where counterpart uniform Ge and abrupt heterojunction TFETs are also shown for compar- ison. A double-gate structure and 10-nm body thickness were used with a 4.8-eV gate work function and 3-nm HfO 2 gate dielectric for low subthreshold swing and high current density [4], [15]. A heavily doped n+ source of 10 20 cm −3 and p+ doped drain of 5 × 10 18 cm −3 were utilized with a p-body of 10 17 cm −3 to improve the ON-current and subthreshold swing and to reduce the ambipolar leakage current [1], [6], [11]. In numerical simulations, the graded Si/Ge heterojunction is assumed linearly while considering physical tunneling models [6], [16]. For the abrupt heterostructure TFET, an optimized p-channel TFET (Si-drain, Si-channel, and Si 0.7 Ge 0.3 -source) [13] with a gate work function of 5.27 eV was utilized to ensure a competitive heterojunction device. The selection of a 0.3 Ge mole fraction and 2-nm gate–source overlap was based on the optimization of a high ON-current, low OFF-current, and steep subthreshold swing [13]. Fig. 1(b) shows the energy-band diagrams of 50-nm graded Si/Ge TFETs along channel surface in on and off states. Under the ON-state condition, the graded Si/Ge TFET has a narrow tunneling barrier to generate a high ON-current. In the OFF state, the tunneling barrier is considerably large to control the leakage current. Notably, a gradually wide and high barrier is observed from the source to the drain in the graded Si/Ge TFET, which is different from that in a uniform Ge TFET. This feature of the tunneling barrier plays a key role in suppressing short-channel effect and OFF-state current in scaled TFETs. 0741-3106/$26.00 © 2011 IEEE