A Multistandard FFT Processor for Wireless System-on-Chip Implementations Ramesh Chidambaram, Rene van Leuken Marc Quax, Ingolf Held, Jos Huisken Department of Electrical Engineering (CAS group), Silicon Hive Delft University of Technology Eindhoven, The Netherlands The Netherlands {marc.quax, ingolf.held, jos.huisken}@philips.com {r.chidambaram, t.g.r.vanleuken}@ewi.tudelft.nl www.siliconhive.com do not provide the performance to support such time critical solutions. The design methodology of the presented Abstract-This paper presents a high performance FFT Application Specific Instruction-set Processor (ASIP) - ASIP. The resulting programmable solution is scalable for henceforth referred to as the AVISPA-Expl - is such that the order of the FFT and capable of satisfying performance the FFT order is scalable in software, and derivatives of requirements of various OFDM wireless standards. The the ASIP for different requirements can also easily be IEEE 802.15.3a Ultra Wideband OFDM - being the most obtained. Hence the fundamental focus of the present work time critical of these standards because of the computation is meeting the demands of the FFT for UWB-OFDM. of a 128-point FFT within 312.5 ns - has been the primary performance target of the scalable ASIP. The resulting ASIP adopts a vectorial Ultra-Long Instruction Word (ULIW) B Silicon Hive sASIPdesign template approach. The design decisions are evaluated with regards to Silicon Hive has developed a proprietary design processing speed, area and power dissipation. methodology and toolset to enable automatic instantiation of an architecture template [2]. All of Silicon Hive's processors are derived from this template, referred to as I. INTRODUCTION ULIW (Ultra Long Instruction Word) technology. The This section states the objectives and the design basic component of the processors is the processing and framework is described. Section II presents design choices. storage element (PSE). A PSE is configurable, and a Processor architecture, system integration issues and general schematic is depicted in Fig. 1. software are subjects of Section III, IV, and V respectively. A characterization of the processor with regard to processing speed, gate count, power dissipation and L LI scalability is shown in VI. Finally, Section VII summarizes the paper. A. Problem description The Fast Fourier Transform (FFT) is an integral part of Orthogonal Frequency division multiplexed (OFDM) wireless communication standards - such as 802.1 1a/g, MEM* 802.16, and 802.15.3a - the requirements of which are tabulated in Table 1. TABLE I. FFT PERFORMANCE REQUIREMENT COMPARISON OFDM standard Commercial name FF1 Time for Figure 1. General schematic of a Processing and Storage Element OFDMI standard Commercialnae izeI computation IEEE 802.11 WiFi (WLAN) 64 4 gs The PSE is a Ultra Long Instruction Word (ULIW)-like IEEE 802.16 WiMax (WMAN) 512 146 gs datapath consisting of several interconnect networks (IN), IEEE 802.15.3a WiMedia (WPAN) 128 312.5 ns one or more issue slots (IS) with associated functional As seen in Table I, the FFT for the Orthogonal Frequency units (FU), distributed register files (RF) and an optional division multiplexed Ultra Wideband (UWB-OFDM) local memory storage (MEM). The design methodology proposal [1] - commercially referred to as WiMedia - for involves automated instantiation of a processor like the high-speed WPAN systems is the most demanding in AVISPA-Expl from a hardware specification, written in a terms of time-criticality as it has an available time span of highly abstract hardware description language called TIM. 312.5 ns for complete computation. Commercially This enables incorporating rapid changes to the hardware available general-purpose programmable DSP processors architecture thus easing design iterations for co-simulation. 0-7803-9390-2/06/$20.00 ©)2006 IEEE 1099 ISCAS 2006