952 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 Extension and Source/Drain Design for High-Performance FinFET Devices Jakub Kedzierski, Member, IEEE, Meikei Ieong, Senior Member, IEEE, Edward Nowak, Thomas S. Kanarsky, Ying Zhang, Ronnen Roy, Diane Boyd, David Fried, and H.-S. Philip Wong, Fellow, IEEE Abstract—Double gate devices based upon the FinFET archi- tecture are fabricated, with gate lengths as small as 30 nm. Partic- ular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investi- gated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabri- cated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing dif- ferent transport properties. Index Terms—(110) transport, double gate, extension doping gradient, extension resistance, external resistance, FinFET, orien- tation dependent transport, raised source drain, silicon epitaxy, thin body, transistor scaling, ultra-thin body, undoped body. I. INTRODUCTION T HE difficulties in shrinking the size of the traditional bulk transistor have prompted the development of a new de- vice architecture in which two gates, one on each side of the body, are used per device. Such double-gate transistors have higher scalability than their single gate counterparts since both gates help to control the potential in the body [1]. From sev- eral double-gate device architectures the FinFET [2]–[5] has emerged as a promising device structure. It combines the critical elements of superior scalability found in all double-gate devices with the manufacturability of conventional transistors. The body of a FinFET device, shown in Fig. 1, consists of a vertical crystal silicon wall, called a fin. The gate wraps around both sides of the fin, creating a channel on each side. The main advantage of the FinFET structure over other double-gate device designs is that the self-aligned gates can be fabricated using a single lithog- raphy and etch step. One of the central challenges in making FinFETs competitive with conventional transistors is enabling high current drive by reducing parasitic series resistance. The device regions that contribute to series resistance: the extension region, the source/drain region, and the silicide are geometrically dif- Manuscript received July 17, 2002; revised December 12, 2002. The review of this paper was arranged by Editor R. Shrivastava. J. Kedzierski, Y. Zhang, R. Roy, and H.-S. P. Wong are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: jakub@us.ibm.com). M. Ieong, T. S. Kanarsky, and D. Boyd are with the IBM Microelectronics Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 USA. E. Nowak and D. Fried are with the IBM Microelectronics Division, Essex Junction, VT 05452 USA. Digital Object Identifier 10.1109/TED.2003.811412 ferent in a FinFET and therefore require modified integration schemes. For example, the extension region in a FinFET has a normal that lies in the wafer plane, orthogonal to the wafer normal, and the conventional extension implant vector. This geometric difference suggests that highly angled implants would be effective in forming uniform extension regions. The source/drain region also requires re-engineering. In the simplest form, as shown in Fig. 1, the FinFET lacks the equiv- alent of a deep source/drain region that makes the formation of low resistance silicide contacts possible. Low resistance con- tacts are still possible by using low barrier silicides [6], or by thickening the fin outside of the gate region with a selective de- position, such as silicon epitaxy. However, both silicon epitaxial regrowth of the source/drain regions and low barrier silicides ideally require well-formed spacers, which separate the fin from the gate but leave the side of the fin accessible. In this paper, highly angled extension implants together with epitaxial raised source/drain (RSD) are shown to yield high performance FinFET devices. Issues relevant to high performance FinFET design including: extension resistance, fin epitaxy, spacer formation, silicide, fin orientation, and short-channel effects are discussed. II. PROCESS CONSIDERATIONS The critical steps in the FinFET fabrication process included sequentially: fin formation, gate stack formation, extension implant, spacer formation, epitaxial raised source/drain, deep source/drain implantation, and silicide. The fin can be formed using spacer image transfer (SIT) [7], [8], or by using trimming techniques such as resist ashing to define fins using optical lithography. In this work the latter approach was used due to its simplicity and the ability to yield a wide range of fin thickness on a wafer. However it is likely that in order to achieve the fin thickness tolerances and pitch values required for manufacturing a SIT process would be required. It is possible to form FinFETs with the (100) oxide orientation on a (100) wafer with the notch in the direction, but such a process requires the fin be rotated by 45 from the standard lithographic orientation. If no such rotation is performed the gate oxide forms on the (110) plane. In both orientations the current carrying direction is a normal to a plane in the same family as the gate oxide surface. Both and directed FinFETs were fabricated in this study. Fins were formed by reactive ion etch (RIE) using a silicon dioxide hard-mask, from a 65 nm thick silicon on insulator (SOI) layer. Gate oxide growth was preceded by a sacrificial oxidation to repair the RIE damage to the fin [3]. In this study the gate 0018-9383/03$17.00 © 2003 IEEE