ParalleX: A Study of A New Parallel Computation Model Guang R. Gao 1 , Thomas Sterling 2,3 , Rick Stevens 4 , Mark Hereld 4 , and Weirong Zhu 1 1 Department of Electrical and Computer Engineering 2 Center for Advanced Computing Research University of Delaware California Institute of Technology {ggao,weirong}@capsl.udel.edu tron@cacr.caltech.edu 3 Department of Computer Science 4 Mathematics and Computer Science Division Louisiana State University Argonne National Laboratory tron@cct.lsu.edu {stevens,hereld}@mcs.anl.gov Abstract This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and star- vation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barri- ers) to dramatically enhance the broad effectiveness of par- allel processing for high end computing. In this paper, we present the progress of our research on a parallel program- ming and execution model - mainly, ParalleX. We describe the functional elements of ParalleX, one such model being explored as part of this project. We also report our progress on the development and study of a subset of ParalleX - the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as a ParalleX process- ing architecture. A design point study of Gilgamesh II and the architecture concept strategy are presented. 1 Introduction Historically as technology has advanced, computer ar- chitecture has changed to exploit the new opportunities offered and to compensate for the exposed weaknesses. Alternative strategies for organizing the computation as well as the architectural structures and system software have been devised to provide governing semantic principles upon which such architecture and programming models are based. For more than a decade, the dominant model of com- putation has been the communication sequential process or 1-4244-0910-1/07/$20.00 c 2007 IEEE. more commonly the “message passing model” represented by various implementations of MPI (e.g. MPICH-2, Open- MPI) adopted because of its applicability to microprocessor based MPPs and commodity clusters. Other models used are multiple threads (e.g. OpenMP), vector, and SIMD, but message passing is dominant. However, as semiconductor technology has continued to evolve, both new opportunities and new challenges have emerged demanding correspond- ing improvements to architecture. Most pronounced is the move to multicore components and the re-emergence of het- erogeneous computing elements such as GPUs and Clear- speed SIMD [2] attached processors. The IBM Cell ar- chitecture embodies both heterogeneous and multicore el- ements [6]. These exemplify but do not fully reflect the increasing need for new programming methods and archi- tecture structures to continue to fully benefit from Moore’s Law. An important objective of this research project has been the exploration and development of a possible new ex- ecution model that will more readily employ the potential capabilities of near term semiconductor technologies while easing the programmer burden. Such an execution model could lead to new programming models and languages, new parallel computer architecture, and new supporting system software. In this paper, we present the progress of our research on a parallel programming and execution model - mainly, ParalleX. We describes the functional elements of ParalleX, one such model being explored as part of this project. Par- alleX principal elements are discussed, including locality, global name space, multithreading, parcels, local control objects, percolation, echo, and parallel processes. We also report our progress on the development and study of a sub- set of ParalleX - the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as